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Dual Core Initialization

Husain Shizan
Associate

I am working on Dual Core SPC58x Series and I face some trouble with Dual core initialization and Usage.

For the Moment it will be very much helpful if you can share a document / Application Note / Example on the Initialization and Usage of Dual Core Architecture.

This discussion has been locked for participation. If you have a question, please start a new topic in order to ask your question
3 REPLIES 3
procolo
Senior
Tran Hung
Associate II

Hello @procolo​ 

I am sorry to post my question in this post. Because I already tried to post my question to ''Q&A" group but it didnt work.

Can you check my question?

I tried to configure eTimer_0 ETC_4 as a source FAULT_0 for eTimer 3. The PA[13] is assigned as an external input fault source. My configuration code is below:

void etimer_config ()

{

ETIMER_0.CH[4].CNTR.R = 1000;

ETIMER_0.CH[4].CTRL1.B.CNTMODE = 0x6U; /* Edge of secondary source triggers primary count till compare */

ETIMER_0.CH[4].CTRL1.B.PRISRC = 0x18U; /* primary count source = IP bus clock/2 */

ETIMER_0.CH[4].CTRL1.B.SECSRC = 0x4U; /* Counter #4 input pin etimer0.ch[4]/ PA[13] */

ETIMER_0.CH[4].CTRL1.B.ONCE = 0U; /* count repeatedly */

ETIMER_0.CH[4].CTRL1.B.LENGTH = 0U; /* count until rolling over */

ETIMER_0.CH[4].CTRL1.B.DIR = 0U; /* count up */

ETIMER_0.CH[4].CTRL2.B.OEN = 0U; /* output disable */

ETIMER_0.CH[4].CTRL2.B.RDNT = 0U; /* disable redundant channel */

ETIMER_0.CH[4].CTRL2.B.INPUT = 0x1U;  /* External input signal enable*/

ETIMER_0.CH[4].CTRL2.B.SIPS = 0x1; /* Positive edge for recounting*/

ETIMER_0.CH[4].CTRL3.B.FMODE = 1;   /* change mode */

ETIMER_0.CH[4].CTRL3.B.FDIS = 1; /* The channel OFLAG output is affected by this FAULT pin. */

ETIMER_0.CH[4].FILT.B.FILT_CNT = 7; /* sample filter counter*/

ETIMER_0.CH[4].FILT.B.FILT_PER = 255; /* input filter period */

ETIMER_0.CH[4].CCCTRL.B.CPT2MODE = 0x2U;  /*Capture 2 Mode Control*/

ETIMER_0.CH[4].CCCTRL.B.CPT1MODE = 0x2U;  /*Capture 1 Mode Control*/

ETIMER_0.CH[4].CCCTRL.B.CFWM = 0x1U;  /*FIFO = 2*/

}

void FAULT_PIN_Configure ()

{

    SIUL2.MSCR_MUX[206].R = 0x1U;

}

When this program operates, the PWM of eTimer_3 already disable, but it is enable when the fault pin PA[13] change the state. Can you review my configuration?

procolo
Senior

ello,

Hello,

Spc5studio 5.8.1 contains example on on how to init and manage dual/tri core on SPC58x platforms. you should:

  • Open the wizard
  • Select 58 Family
  • Select desired MCU
  • select Duall/Tri core test application

Please note :

SPC58 package support is not released by default but it's only for selected customers. Please send a mail to credentials@spc5studio.com to get access to this package.