2016-07-08 05:05 PM
Greetings, currently i am working on my thesis and i am planning to use this IC (STA321MP) for my proyect as it fits the requierments that i am proposing for it, but there are some specific points and doubts that i can not solve along side the data sheet so that�s why i am writing this request. The questions goes as follows:
2) How does the PLL (phase locked_loop) ratio is program orr set? is not very clear on the data sheet.
3) What is the purpouse of the PLL_BYPASS pin ? Its functionality overall. 4) The subject around the PDM_CLK and how to obtain the CKOUT frequency is not very clear for me, could you please help me to understand it in a simpler way. 5) The sampling frequency that is said on the datasheet of the STA321P supports a 2.8224Mhz frequency with a internal fixed clock of 90.3168 hz, Is it a fixed default value? is it variable or i can be set apart? Time is of scense for me, i would apreciate any help you can provide me. Thanks before hand. Good Day. #sta321mp #audio-processing2016-07-10 11:06 PM
Hello Carlos,
The STA321MP is an audio product. In order to have a more appropriate answer, I recommend you to create a similar post in the audio section. Here is ahttps://my.st.com/public/STe2ecommunities/analog/Lists/Audio%20Amplifiers/AllItems.aspx
. Sorry for the inconvenience, and don't hesitate to come back for questions related to op-amps/comparator or current sensing products. Regards, Sylvain