STM32 MPUs Products and hardware related

I know this is probably a really stupid/noob question but I was trying to flash the STM32MP157D-DK1 board I have for the first time following the following guide:https://wiki.st.com/stm32mpu/wiki/STM32MP15_Discovery_kits_-_Starter_Package I ran into an issue where it started the flash and then couldn't reconnect.  I did find this article that seems to describe exactly the issue I'm having:https://community.st.com/t5/stm32-mpus/faq-stm32mp1-stm32cubeprogrammer-usb-reconnect-error-at-stm32mp1/ta-p/49263 It recommends: In Uboot shell run a Dfu command : STM32MP> env set dfu_alt_info "DDR ram 0xC0000000 0x20000000" STM32MP> dfu 0 ram 0  Unfortunately, I don't know how to run a uboot shell to try this.  I know this is probably a really stupid problem . . . but I'm also hoping that means it has an easy solution as well.  Any help you can give me would be greatly appreciated.  Thanks!

Dear all,I'm currently using the STM32MP157F-DK2 series, and I'm trying to use the ADC1 and ADC2 in dual regular simultaneous mode triggered by TIM2 out event. Also, I used one DMA stream (DMA2_stream0) to read the ADC values of the Common Data Register (ADC_CDR) as it is indicated in the MP157F reference manual:This is how I'm starting the ADCs:if(HAL_ADC_Start(&hadc2) != HAL_OK){/* Start Error */Error_Handler();}if (HAL_ADCEx_MultiModeStart_DMA(&hadc1, (uint32_t *)adc_buff, 8) != HAL_OK){/* Start Error */Error_Handler();} if (HAL_TIM_Base_Start(&htim2) != HAL_OK){Error_Handler();}Also, I have checked the ADC's registers, to make sure the configuration is correct. This is the configuration for the ADC1 and ADC2:static void MX_ADC1_Init(void){/* USER CODE BEGIN ADC1_Init 0 *//* USER CODE END ADC1_Init 0 */ADC_MultiModeTypeDef multimode = {0};ADC_ChannelConfTypeDef sConfig = {0}hadc1.Instance = ADC1;hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;hadc1.I

Hi,compiler bug while building m4-projects from `https://github.com/STMicroelectronics/oe-manifest/tree/mickledore` The compiler series 11.2 has a internal compiler bug, so that I cannot compile the yocto mickledore with st settings. The issue is here `https://github.com/STMicroelectronics/meta-st-stm32mp/blob/mickledore/recipes-devtools/gcc-arm-none-eabi/gcc-arm-none-eabi_11.inc` - buggy compiler is used.Here are some bug reports on this topic:https://bugs.launchpad.net/gcc-arm-embedded/+bug/1970029https://bugs.linaro.org/show_bug.cgi?id=5825Here the answer from arm:https://community.arm.com/support-forums/f/compilers-and-libraries-forum/52623/gcc-11-2-arm-none-eabi-internal-compiler-error-illegal-instructionRegardsUwe OS: Ubuntu 22.04/20.04Arch: x64 | /home/uwe/Projects/git/pVentRefresh/yocto/yocto/build-openstlinuxeglfs-stm32mp1/tmp-glibc/work/stm32mp 1-ostl-linux-gnueabi/m4projects-stm32mp1/1.6.0-r0/git/Projects/STM32MP157C-EV1/Demonstrations/AI_Charact er_Recog

We are using MuRata Module LBEE5HY1MW on our custom board based on OSD32MP157F. We are using Octavo Systems OSD32MP1 Debian SDK v3.0 based on Debian 11 and OpenSTLinux Kernel version 5.10.10.We've integrated following 1MW firmware files from murata github to OSD32MP1 Debian SDK.BCM4345C0_003.001.025.0172.0344.1MW.hcdcyfmac43455-sdio.1MW.txtcyfmac43455-sdio.bincyfmac43455-sdio.1MW.clm_blobHere are the hardware pin connections between 1MW BT module and SiP: 1MW BT module OSD32MP157F SiPBT_UART_RTS => USART2_RTS (PA1)BT_UART_CTS => USART2_CTS (PE15)BT_UART_RXD => USART2_TX (PA2)BT_UART_TXD => USART2_RX (PA3)We noticed that RTS/CTS pin connection is wrong and we can not change it on the current board version.We want to configure the USART2/BT with “no hardware flow control�? which require RTS/CTS signals to be pulled active low.To integrate 1MW module on USART2 port, we’ve made following changes in kernel device-tree, removed RTS/CTS from pinctrl block and applied pull-dow

Hi there, We are using Murata Module LBEE5HY1MW on our custom board based on STM32MP157A. And we are using OpenSTLinux Kernel Version 4.19.9.We integrated LBEE5HY1MW's bluetooth with BlueZ v5.50 driver.And the HW connections between LBEE5HY1MW BT and STM32MP157A,BT_UART_CTS => USART7_RTS (PE9)BT_UART_RTS => USART7_CTS (PE10)BT_UART_RXD => USART7_TX (PE8)BT_UART_TXD => USART7_RX (PE7)Our Device Tree Configuration as below:&pinctrl { uart7_pins_a: uart7-0 { pins1 { pinmux = <STM32_PINMUX('E', 8, AF7)>, /* USART7_TX */                                                 <STM32_PINMUX('E', 9, AF7)>; /* USART7_RTS */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { pinmux = <STM32_PINMUX('E', 7, AF7)>, /* USART7_RX */                        &nb

We are running a stm32mp151c with stm32mp linux built with yocto. The kernel complain that the cpu0 clocl-frequency is not set, but the patch layers/meta-st/meta-st-stm32mp/recipes-kernel/linux/linux-stm32mp/5.10/5.10.116/0022-ARM-5.10.116-stm32mp1-r2.1-DEVICETREE.patch removes DTS clock-freuency setting line 3889: -         clock-frequency = <650000000>;From release notes STM32 MPU OpenSTLinux release note - v4.0.0 - stm32mpu for 5.15 I found "BL2 always boots at 650MHz" and it seems the kernel should probe for cpu clock-frequency. The board boots, but we get these log entries that makes me wonder if we miss anything in DTS:"Starting kernel ...[  0.003140] /cpus/cpu@0 missing clock-frequency property[  2.666366] stm32-cpufreq stm32-cpufreq: Failed to get chip info: -517"Could anyone give me a hint where I can find more info about this patch and the background for removing the DTS cfg line "clock-frequency = &l

Hi guys,The schematics for STM32MP15x-EVAL board (MB1263) uses a level shifter for SDcard from NXP (IP4856CX25) that is now obsolete. I found 2 close alternatives:ST6G3244MEBJR from ST, with one pin only (C4) different from IP4856TXS0206YFPR from TI, with 5 pins less then IP4856Questions:Is it possible to use the ST6G3244 from ST replacing the IP4856CX25 from NXP? If so, is it a direct replacement (with pin C4 of STG3244 tied to GND)?I noticed that the NXP part has a wider host side voltage range up to 3V3 than the ST part. I don't have the MB1263 board here to measure, so I need to know what is the Voh of the SDcard lines in STM32MP157 in MB1263. Can anyone help me on this?Is it possible to use the TXS0206 from Texas which have a wider host side voltage range compatible with 3V3?Is there any other alternative to replace the IP4856CX25 from NXP?Thank you guys in advance for any light on this topic.

I'm trying to get to know stm32mp1 while making a board for this thing.While using the default image provided by manufacturer seems to work. The kernel used is old compared to the current ST BSP and support from them isn't exactly great so I'm trying to migrate to the latest BSP. This isn't going so well.Following instructions found in the wiki. I've managed to compile it but when trying to run, it just stops at 'starting kernel'. Recompiling with LL_DEBUG and EARLY_PRINTK, resulted in some more info.The lines that seems to show an issue are:[ 1.599531] i2c_dev: i2c /dev entries driver [ 1.606005] syscon-reboot: probe of reboot failed with error -22 [ 1.733737] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping .... [ 2.031116] irq: no irq domain found for gpio@54004000 ! [ 2.036565] gpio-keys joystick: Found button without gpio or irq [ 2.057386] gpio-keys: probe of joystick failed with error -22 [ 3.458283] Warning: unable to open an initial console. [ 3.465913] Freeing unused kern

I'm trying to testing secure boot on a STM32MP157F-EV1. To do so, I planned to use the fuse override command to test secure boot without having to actually burn the OTP 24-31 with the public key hash.But it appears that fuse override command is not working properly: after overriding cache to store publicKeyhash.bin, the read is exempt of the key. (note: the publicKeyHash_values is a placeholder)STM32MP> fuse override 0 0x00000018 publicKeyhash_values Overriding bank 0 word 0x00000018 with publicKeyhash_values[0] Overriding bank 0 word 0x00000019 with publicKeyhash_values[1] Overriding bank 0 word 0x0000001a with publicKeyhash_values[2] Overriding bank 0 word 0x0000001b with publicKeyhash_values[3] Overriding bank 0 word 0x0000001c with publicKeyhash_values[4] Overriding bank 0 word 0x0000001d with publicKeyhash_values[5] Overriding bank 0 word 0x0000001e with publicKeyhash_values[6] Overriding bank 0 word 0x0000001f with publicKeyhash_values[7] STM32MP> fuse read 0 0x00000018 8

Custom board. Boot log as belowextlinux.conf:MENU BACKGROUND /splash_landscape.bmpTIMEOUT 20LABEL OpenSTLinuxKERNEL /uImageFDTDIR /INITRD /st-image-resize-initrdAPPEND root=PARTUUID=e91c4e10-16e6-4c0e-bd0e-77becf4a3582 rootwait rw console=${console},${baudrate} dyndbg="file drivers/usb/core/hub.c +p"adding the dyndbg following: https://wiki.st.com/stm32mpu/wiki/How_to_use_the_kernel_dynamic_debug#Debug_messages_during_boot_processums 0 mmc 0Did not show /media/$USER/bootfs.Any hints/ideas/suggestion to (enable) debug the root cause?the dt of u-boot is the same as for the kernel.The kernel uImage and DT blob were copied to bootfs.The rootfs /lib/modules was also updated, probably not needed as the  SD card was created with the files and tools of the starter package in ECO 5.0.0. and modules were not changed.U-Boot 2022.10-stm32mp-r1 (Oct 06 2023 - 20:22:10 +0800)CPU: STM32MP157AAA Rev.BModel: STMicroelectronics custom STM32CubeMX board - openstlinux-6.1-yocto-mickledore-mp1-v23.06.

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Hello,I read the AN5122 which explains in chapter 4.2, that the RAM lane byte 0 must be connected to byte 0 of the MP1 and that the bits swapping is not possible. However on the EV1 board, the bits inside byte 0 lane are swapped. Furthermore, i do not know how to identify byte 0 at the ram chip, since i want to use two of them.For the design I am working on, I need 1GB DDR3L RAM, split in two 512MB RAM chips. In the AN I found this picture:I'd like to place the two chips next to each other, using STM32MP1's Byte 2 / Byte 0 for chip 1 and Byte 1 / Byte 3 for chip 2. Is this possible to do?Thanks

Dear experts. ​we plan to use a STM32MP157, where the A7 core should have 512MB DDR RAM, and theM4 core 16 MB. What options exists, to give the M4 core that 16 MB of RAM?From the DS, i understand that the DDR RAM of the A7 is not accessible for the M4. Is that right?external QSPI PSRAM, would be low cost and low pin count. From the DS, the QSPI interface is only for Flash, not for PSRAM?external SRAM/SDRAM via the FMC? Could the M4 core occupy the FMC, while the A7 core using DDR?external SPI RAM, would be the slowest variant, but should be always possible.Is there an application note, showing how more then a MB RAM is added to the M4 core in an STM32MP15x?Best regards,Michael

Hi,We are using the meta-st-stm32mp layer in out Yocto build system. We have had the system run on the Dunfell distribution up until now with OPTEE as the secure OS.For Dunfell the version of OPTEE is 3.12 along with patches from ST, a we tried to upgrade to Kirkstone which uses OPTEE version 3.16. From what we see the secure storage is no longer compatible with the new version:We get errors like this when using the 3.16 version and the secure storage has been created with 3.12# optee_example_hello_world optee_example_hello_world: TEEC_Opensession failed with code 0xf0100001 origin 0x3We did another test with the official OpenST distribution on a DK2 board fist running Dunfell then upgrading to Kirkstone and we get the same results.We have asked upstream OP-TEE is there is an issue between the versions for backwards compatibility related to secure storage:https://github.com/OP-TEE/optee_os/issues/6296After this we went further and did a test with the upstream version of OP-TEE 3.12 and

Can not Flash STM32MP157FAD. with CubeProgrammer, and StarterPackage Image. First 2 files download ok, then get "Reconnecting the device...", and it never reconnects. And the MPU reset, with CubeProgrammer can download first 1 file. Windows11 drops the USB-DFU device. How to fix?

Good. I am trying to load the system to my stm32mp157c-dk2 using STM32CubeProgrammer software, but I get the same error when loading partition 13 every time. The error is as follows: Error: failed to download Segment[0] Error: failed to download the File Error: Download partition 0x13 failed Error: TSV flashing service failed Here's the whole process: magno@magno-Latitude-3380:~/Descargas/en.FLASH-stm32mp1-openstlinux-5.15-yocto-kirkstone-mp1-v22.06.15/stm32mp1-openstlinux-5.15-yocto-kirkstone-mp1-v22.06.15/images/stm32mp1$ STM32_Programmer_CLI -c port=usb1 -w flashlayout_st-image-weston/trusted/FlashLayout_sdcard_stm32mp157c-dk2-trusted.tsv ------------------------------------------------------------------- STM32CubeProgrammer v2.14.0 ------------------------------------------------------------------- USB speed : High Speed (480MBit/s) Manuf. ID : STMicroelectronics Product ID : DFU in HS Mode @Device ID /0x500, @Revision ID /0x0000 SN : 002B001F343851053833

Hello,We are designing a custom board with the "STM32MP157FAC1" MPU.Would it be possible to get the die to BGA package pin delays for the DDR3 and the EMMC interfaces ?The AN5122 seems to only have track lengths. Our PCB track layout has some constraints that prevent us from completely copying the reference design layout for DDR. Another post mentioned an Excel table but can't find it in the documentation page for the IC.Thank You.Aron.

I have a system (built using yocto kirkstone) working with the bootchain TF-a -> sp_min -> uboot when loaded from the sdcard and from the emmcI have tried to boot into uboot by loading it directly into memory (as a precondition to the use it to flash the emmc) by following this guide: https://wiki.st.com/stm32mpu/wiki/How_to_load_U-Boot_with_STM32CubeProgrammerI have used the correct tf-a binary and it does manage to load SP_MIN (I get all the SP_MIN traces), but the boot just hangs afterwards.Does u-boot require some special compilation flag in order to be used in this manner?

Hello @everyoneI have a OSD32MP1-BRK mpu board. I want to test maximum gpio toggle speed. Currently i used libgpio and using this code i achieved 4.1 us (microsecond) between rising and falling edge of pulses.This is too slow as per our requirement.  I need in nano second.I have attached waveform. In rpi getting approx 15ns.Thanks and regardsKundan Jha

Hi all,Our product uses an STM32MP153 processor, booting its first and second stage bootloaders (TF-A and uboot respectively) from QUADSPI NOR FLASH. It boots Linux from eMMC. The NOR FLASH we have been using are either IS25LP016D-JNLE or AT25SF161B-SSHB-B which are both 16Mbit.We are experimenting with using a larger 32Mb NOR FLASH due to customer request. We have built a batch of PCBAs with IS25LP032D-JNLE instead of the IS25LP016D.However on 4 out of 12 boards, we see the below:- Programming works ok, all stages are flashed onto the respective parts. stm32 cube programmer reports success- When rebooted after programming, the MP1 still boots in DFU mode.- Checked BOOT mode pins and they are set to 001, not 000, so its not the boot mode.- NORFLASH chip has been written to and read back correctly and program has been verified, so there is no data corruption- Re-ran stm32 cube programmer several times, and MP1 always reboots in DFU mode- We suspect that there is a timing

Hello, I've just migrated from V4.1.0 dev package to V5.0.0 and the LCD SPI ilitek 9486 does not work anymore.Configuration: STM32MP157A-DK1 with 3.5 LCD SPI touchscreen. Starter Package loaded with stm32mp157c-dk2 config. Linux kernel recompiled with ili9486 module and uploaded. Device tree file "stm32mp157c-dk2.dts" modified with spi5 added and display and uploaded.Please, how can I do to recover the LCD SPI that worked on previsous dev package? 

Following this:https://wiki.st.com/stm32mpu/wiki/How_to_configure_U-Boot_for_your_board As the default config used stm32_defconfig.At the step make menuconfig disabled PMIC in device driver -> power  and  enabled regulator power .Though, this  causes compile errors when building u-boot.Created a defconfig file for the board but not a new vendor-board folder assuming just to base the board as a variant of existing ST board.  In other words using make stm32mp157a-board-mx_defconfig.In the config file :CONFIG_TARGET_ST_STM32MP15X=y Does this need to be set to "n" in case of using a board based on the STM32MP1 ?Is disabling PMIC in u-boot actually required to boot a discrete powered board ?

Hello      We are using timer peripheral in STM32MP157 Cortex -A7 core 0 processor. In this, we enabled TIM2, TIM3, TIM4 in RCC APB1 peripheral enable for MPU set register, now we unable to use these timers (not getting interrupts) in Cortex -A7 core 0 processor. But we enabled these same timers in RCC APB1 peripheral enable for MCU set register, at this time getting interrupts in Cortex -A7 core 0 processor.       So, any reason these timers (TIM2, TIM3, TIM4) enables in MCU set register to use in Cortex -A7 core 0 processor. remaining all peripherals are works with enables same MPU set register. regards srikanth

Same or related postshttps://community.st.com/t5/stm32-mpus-products/op-tee-error-on-new-v5-0-0-sdk/td-p/578239/page/2https://community.st.com/t5/stm32-mpus-products/op-tee-error-tzc-permission-failure-on-new-v5-0-0-sdk/m-p/584339Custom STM32MP157AAA3 board,  512MB. TF-A OP-TEE in SYSRAMTwo outcomes.[a] building u-boot with stm32mp1_trusted_defconfig : boot loops around (restart), does not even reach u-boot[b] building u-boot with stm32mp1_defconfig: dump_fail_filter:425 Violation @0xdfb19000, non-secure privileged write, AXI ID 480This area  was firewalled in fw-config.dts based on the Wiki how to configure FW-CONF and also added as a reserved area in TF-A, OPTEE and u-boot DT,  Though u-boot (or something else for that matter) tries to access this area ?Does this violation have anything to do witha. conf.mk  in OP-TEE or the OP-TEE DT ?  (memory reservation was added)b.  FW-CONFIG DT?  (Firewall for this region was added)c.  U-BOOT  DT?&nb

Hello everyone,I am trying to apply the hello world example from stm32MP1 workshop. everything works fine for me. However, when I try to run the application inside stm32mp1 it shows me this message. version `GLIBC_2.34' not found.I tried to install newer version of GLIBC but without any suncess.could you please tell what to do here.