STM32 MCUs Embedded software

Hello,I noticed that in the STM32Cube_FW_H7_V1.13.0 distribution, the folder \Drivers\CMSIS\DSP\Lib has disappeared.Is there a document available that explains how to compile these libraries, and what are the options and defines to set for an STM32H743?Thank you.

Hi ST expertSTM32G473cbt6 and STM32G474cbt6 are pin-to-pin compatible, can their software projects be designed into one project?

Post edited by ST moderator to follow the community rule to post a code snippet: How to write your question to maximize your chances to find a solutionI need to use scan sequence of 3 ADC channel  and DMA transfer of the 3 ADC value .The 3 channel are:sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;sConfig.Rank = ADC_REGULAR_RANK_1;sConfig.Channel = ADC_CHANNEL_VREFINT;sConfig.Rank = ADC_REGULAR_RANK_2;sConfig.Channel = ADC_CHANNEL_15;sConfig.Rank = ADC_REGULAR_RANK_3; but doing this the HAL_ADC_ConvCpltCallback is called only once. if I change the ADC_CHANNEL_15 with   ADC_CHANNEL_VREFINT  everything is working correct. Why ? 

I am using STM32H753ZI and trying to bring up Ethernet (LAN8742, RMII) using HAL + lwIP in NO-RTOS  mode. I generated the code using STM32CubeMX with ETH enabled (RMII) and lwIP enabled (WITH_RTOS disabled, static IP). The PHY link comes up and RJ45 LEDs blink, but the board does not respond to ping and no ARP entry is created on the PC (Destination Host Unreachable). I have placed ETH descriptors and RX buffers in D2 SRAM, enabled MPU and D-Cache, verified RMII_REF_CLK to PA1, selected the LAN8742 PHY driver, and I am calling MX_ETH_Init(), MX_LWIP_Init(), and processing lwIP in the main loop. The FreeRTOS-based STM32H743 Ethernet example works, but I specifically want a HAL-only .

After I configure EP1 to the double‑buffered mode, debugging reveals an issue inside stm32g4xx_hal_pcd.c. At line 1761, the endpoint register value is read. After executing PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); to clear the interrupt flag, the actual register content has already been updated. However at line‑1906, (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); still receives the register value captured before interrupt‑flag clearing. This triggers incorrect conditional judgements inside the HAL_PCD_EP_DB_Transmit() function.Probable root‑cause: When transmitting data for the first time under double‑buffered setup, USB_EPStartXfer populates both buffers by default. After Buffer‑0 finishes transmission and triggers an interrupt, the program reads register data at line‑1761 of stm32g4xx_hal_pcd.c. Right after this read operation, Buffer‑1 also completes its transmission and updates the endpoint register. Since HAL_PCD_EP_DB_Transmit uses the stale register value obtained earli

The code I’ve written in main.c for a program on NUCLEO H7S3L8 works perfectly fine, but on NUCLEO F767ZI goes into hardfault mode when reaching line 455 “mfcc_compute(mfcc_left, audio_buffer_16bit_left, mfcc_feature_left);” (more precisely, inside this function, at line 263 “float last = (float)audio_data[0] / (1 << 15);”). Can someone tell me how to solve the problem? I’ve declared arrays static to not go into stack overflow. Can someone tell me how to solve the problem? (Int_mic_F7 is the project for NUCLEO F767ZI while audio.zip is the project for NUCLEO H7S3L8) 

In stm32f0xx_hal.c:/** * @brief Initialize the MSP. * @retval None */__weak void HAL_MspInit(void){ /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */} But this must not be implemented in a User file, because there is already an implementation generated by CubeMX in stm32f0xx_hal_msp.c:/** * Initializes the Global MSP. */void HAL_MspInit(void){ /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE(); /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */} So implementing a HAL_MspInit() in a User file - as the comment in stm32f0xx_hal.c suggests - will cause a “multiple definition” Linker error!

Hi all,I'm working on the STM32H747I-DISCO (CM7 core, bare-metal LwIP without RTOS, polling mode via MX_LWIP_Process()). Goal is simply to get the board to respond to ping from my PC over Ethernet.Hardware done:Solder bridge rework completed per UM2411 Table 5: SB8 closed / SB21 open (PC1 → ETH_MDC instead of mic DOUT), R87 open / SB17 closed (PE2 → ETH_nINT instead of mic CLK)Software config:ETH set to RMII mode in CubeMX, all 9 RMII pins showing green in Pinout view (PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG12, PG13) LWIP middleware enabled, static IP configured (matching my PC's subnet), no DHCP USART3 used for debug output via Putty Everything runs on CM7 only; CM4 isn't touching ETH/LWIPSymptom:The code intermittently jumps into HardFault_Handler(void) — not on every run, which points to a timing/cache-related issue rather than a hard config error. When it doesn't crash, ping still doesn't get a reply./* Private user code ---------------------------------------------------------*//*

I’ve set pin PD8 and PD9 for USART3 and I’ve checked the baud rate that is 115200, but usart3 does not transmit data to serial monitor yet. How can I solve the problem?

I'm working with an STM32F070 and trying to verify the Independent Watchdog (IWDG). My expectation is that if the watchdog is not refreshed, the MCU should perform a system reset after the timeout expires.The IWDG is configured as follows:MCU: STM32F070 Clock: HSI = ON (System Clock) LSI = ON (for IWDG) IWDG configuration: Prescaler = 256 Reload = 4095 Window = 4095 The watchdog is initialized using HAL_IWDG_Init().To force a timeout, I intentionally do not refresh the watchdog: // IWDG_KICK();while (1){ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, GPIO_PIN_RESET);}The full initialization is: hiwdg.Instance = IWDG;hiwdg.Init.Prescaler = IWDG_PRESCALER_256;hiwdg.Init.Reload = 4095;hiwdg.Init.Window = 4095;HAL_IWDG_Init(&hiwdg);According to the reference manual, with Prescaler = 256 and Reload = 4095, I expect a wat

Hi, everyone,I'm trying to implement USB CDC on an STM32H5E5 board using the classic USB device middleware. I followed another community thread that provides the steps to do this: How to Use STMicroelectronics’ Classic USB Device Middleware with the New STM32 Families:  When compiling the code, I encountered some errors at this point in the library: USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev){pdev->pData = &hpcd_USB_DRD_FS; HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x40);HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x80);HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , CDC_IN_EP , PCD_SNG_BUF, 0xC0);HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , CDC_OUT_EP , PCD_SNG_BUF, 0x100);HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , CDC_CMD_EP , PCD_SNG_BUF, 0x140); return USBD_OK;}The error messages are as follows Description    Resource    Path    Location    Type'PCD_SNG_BUF' u

Hi ST Community,I am currently working on an analog sensor acquisition project using the NUCLEO-N657X0-Q (STM32N657X0) board on STM32CubeIDE (version 1.19.0). I am attempting to read a Keyes pressure sensor via ADC1 on PA1 (ADC1_INP1).Physical Wiring & Setup Sensor Connections: The pressure sensor is physically wired to: VCC -> Board 3.3V GND -> Board GND Signal Out -> PA1 (bridged with a 1/2 resistor divider to ground to ensure the voltage never exceeds 1.8V). CN12 Jumpers Connected: Pin 13 / Pin 14 (VDDA1V8) is connected with a jumper cap to supply 1.8V to VDDA. Pin 11 / Pin 12 (VDDIO) is connected with a jumper cap.  STM32CubeMX Configurations VREFBUF: Configured as Disable (since the NUCLEO board provides an external 1.8V reference to VREF+). Security & RIF (RIFSC Panel): ADC1: Configured as Non-Secure, Unprivileged (unchecked), Unlock (unchecked), and assigned to the Application context. GPIOA: Configured as Non-Secure, Unprivileg

When using the ISP IQTune application to generate ISP parameters for the STM32N6 DCMIPP, the Auto White Balance expresses an error that I believe is incorrect. The error claims that AWB cannot start becase the R/B ratios for white balance must decrease, as the color temperature increases. The ratio IS decreasing, as shown in the image below.When the temperature is 5100K, the R/B ratio is 2.1/1.9 = 1.105When the temperature is 3800K, the R/B ratio is 2.3/1.9 = 1.210Thus, as the temperature increases, the R/B ratio decreases. Either this is wrong, or I’m missing a key component of this calibration process. 

I am using SPI6 on an STM32H562 to write data to a WS2812 LED strip. The following code is called once per second to  write the data: LOGIF ("bytes left=%d", GPDMA1_Channel2->CBR1); LOGIF ("TXC %d", (WS2812_SPI.Instance->SR & SPI_SR_TXC) != 0); LOGIF ("ready=%d", HAL_SPI_GetState(&WS2812_SPI)== HAL_SPI_STATE_READY); if (HAL_SPI_GetState(&WS2812_SPI) != HAL_SPI_STATE_READY) { LOGIF ("error=%d", HAL_SPI_GetError(&WS2812_SPI)); HAL_SPI_Abort (&WS2812_SPI); } HAL_SPI_Transmit_DMA (&WS2812_SPI, spi_bytes, RESET_BYTES + nvalues * BYTES_PER_FRAME); Here is the log output for the first two calls:[101] ws2812 75: bytes left=0[101] ws2812 76: TXC 1[101] ws2812 77: ready=1[201] ws2812 75: bytes left=0[201] ws2812 76: TXC 1[201] ws2812 77: ready=0[201] ws2812 79: error=0The first time, GetState reports READY, but the second time it does not, even though bytes_left is zero and TXC is 1, so an Abort is required before the next transmit. Unfortunat

I currently have two boards equipped with different specific models of N6, namely STM32N647X0H3Q and STM32N657X0H3Q. I have an IDE project for testing the memory-mapped functions of each of these two chips.The problem lies in that this project can be implemented on the STM32N647X0H3Q in a manner similar to:  data = *(volatile uint8_t *)0x70100000;Such code reads the content from the external FLASH. However, on the STM32N657X0H3Q, it is impossible to read. The specific manifestation is that when I run this line of code in the debug mode, the program directly jumps tovoid SysTick_Handler(void)and the debugging connection is disconnected, as shown in the following figure. I have wondered whether it was an issue with the external FLASH soldering, or a problem with the PCB traces (my two circuit boards were not produced on the same PCB. The circuit board with STM32N647X0H3Q was purchased from the internet, while the one with STM32N657X0H3Q was designed based on the schematic diagram of the

Hi ST Team,I’ve been using STM32G473VET3 for my product for the past 2 years.Right now I’m testing the code which I’ve freezed an year ago. But it enters uart error callback as soon as it calls HAL_UART_RECEIVE_IT function.(Overrun error continuously even after clearing it, Also no data is sending in that line).Hence I’ve generated new code in the cubemx also. In that also same problem arises whenever HAL_UART_RECEIVE_IT is called.IDE version : 1.18.1MX version : 6.14.0G4 package version : V1.3.0

Hi everyone,I want to read data from an SPI slave using SPI3 while the MCU is in STOP2 mode.The communication protocol requires me to transmit a command before receiving the response.I configured LPBAM according to the following YouTube tutorial, and my CubeMX/LPBAM configuration is shown in the attached screenshots.My observations are:If I use only the “Transmit Data” node, everything works correctly. If I add a “Receive Data” node after the transmit node, the SPI transaction stops when it reaches the receive node. However, the “LPTIM1_CH1” output continues to generate trigger signals. If I replace them with a single “Transmit Receive Data” node, neither SPI nor LPTIM1_CH1 works.Could you please explain what might be causing this behavior? Is there any additional configuration required to use the “Transmit Receive Data” node in LPBAM with SPI3 in STOP2 mode?Thank you. 

0x0BF97000 (system bootloader base per AN2606): the jump appears to succeed (In Debug reaches the bootloader region), but execution then breaks at an address inside the bootloader ROM with no further progress and no USB enumeration. The hardware boot path works correctly. The problem is purely on the software-jump path.I created an empty project in sample you can download and test it. I also attached my option bytes (i think everything is default).MCU: STM32H573 (also tested h523)/** ****************************************************************************** * @file dfu_jump.c * @author Uğur Tümer * @brief See dfu_jump.h. Implements the magic-word + soft-reset path into * the STM32H523 system bootloader (USB DFU on PA11/PA12). ****************************************************************************** */ #include "dfu_jump.h" /** Magic word stored in TAMP_BKP0R between the request and the next boot. */ #define DFU_JUMP_MAGIC 0xDEADB007UL #define BOOT

Hello!I have been trying to review and fix the configuration of my Ethernet LwIP+FreeRTOS STM32 project and I would like to ask more experienced people if I have correctly chosen memory locations, modified the linker script, configured MPU and a few other things. My project uses STM32F746VGT6 MCU that has 320KB of RAM and 1024KB of flash memory:MEMORY{ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K} Since this project uses Ethernet peripheral and LwIP library, a few memory sectors need to be defined: one for Tx Descriptor, one for Rx Descriptor, one for RX POOL and one for LwIP heap.I have set Tx and RX Descriptor addresses to 0x20048000 and 0x20048100 and checked in debugger that each one of them takes 160B of space, so 256B is more than enough to store a single Descriptor.I decided to store memp_memory_RX_POOL_base under 0x20040000 address in 32KB section. With ETH_RX_BUFFER_CNT defined to 16U, size of memp_memory_RX_P

My STM32F429 LWIP project stops all network comms after running for a few hours.  I am hoping that this is a known bug with a known fix. But I would appreciate any insight that anyone can provide.I have a CubeMX generated project using LWIP and FreeRTOS running on an STM32F429. I have an ethernet interface using a LAN8742A.After running for a few hours my project stops communicating and does not recover. I think I have ruled out any kind of memory or buffer exhaustion.  I suspect a race condition of some sort.Every time the comms stop, all of the RX descriptors are owned by the CPU and the ethernet RX descriptors are stuck in this same pattern.The numbers change but RxDescIdx is always (RxBuildDescIdx + 1).  And the counts are always = 1. heth->RxDescList->ItMode =          1    RxDescIdx    =          27    RxDescCnt =          1    RxDataLength =      118    RxBuildDescIdx =    26    RxBuildDescCnt =    1    pRxLastRxDesc    =      7734049    FreeRTOS is still running the idle

Hi All,I am using STM32U375RETx on in my project on a custom board. I am using 8 channels on ADC1 and 3 on ADC2. I want to scan all the channels using DMA. I have configured the ADCs in scan conversion mode using dma and have also configured the gpdma channels to connect with the ADCs.My issue is that I am unable to trigger a scan using software trigger. I am able to trigger a scan only once and then if I scan again, the adc callback is triggered. I verified my adc and gpdma logic by switching from software triggered dma scan to timer event triggered dma scan. This worked and the timer was able to always trigger the adc and update the callback to process the adc data. Could anyone please share what would be an example code for U3 to use software triggered adc dma. The github examples show only for timer trigger and not software trigger[link].Below is a cleaned up version of my main.c I appreciate any suggestions!Thanks!/* USER CODE BEGIN Header *//** ***********************************

Hi all, Experiencing yet another hurdle using the STM32N6: I am running into the issue where if I run the VENC as the JPEG encoder, where I previously found out how to properly run it in the first place, I get issues in the I2C slave communication…! Okay, what do I mean…i2c is configured as a slave. I receive/send all data via. DMA First stop for both directions of communication is the `HAL_I2C_AddrCallback` Maximum burst length of any i2c communication on my bus is 256 bytes The above mentioned limitation works very good and without issues, if I do not have the VENC running Problems arise, when I turn on the VENC, encoding each 2nd frame on PIPE1 that comes in through the DCMIPP. It is configured to convert one frame of ARGB24 into a JPEG. I used the middlewares from https://github.com/STMicroelectronics/STM32CubeN6/ and snippets from the VENC_JPEG_Encoding example (commit 8ab3b641, which is the latest as of writing). A list of some problems that I encounter, observed in parallel with

Hello everyone,I am currently working on a project on Nucleo F756ZG where I need to :Use SAI1A and SAI2B to send audio data at the same time using TDM with 8 slots each SAI parameters are 128 bits data frames (so 16 bits per slot) Audio frequency 96k Master mode Use of HAL_SAI_Transmit_DMA to send the dataI managed to configure the SAIs, send and monitor the output data and it is working well but I noticed (an obvious I guess) latency between the payloads of the signals, between the 2 calls of the HAL_SAI_Transmit_DMA function, as you can see on the screenshot (12 us approximately). I would like to reduce this latency under 1 microsecond if possible. During my experimentations I noticed it was possible to set one SAI as master and the other one as its slave and only call HAL_SAI_Transmit_DMA once, but haven’t managed to make it work for now. Is it really possible ? I am looking for a code example to be sure to setup the SAIs properly. I can share more details of my code if necessary. T

I have read these forums and I see some have successfully got the F407 connected to KSZ8863 working. I am trying to do a simple non managed switch RMII PHY connection to the third port with no luck. I have confirmed the 50mhz clock input to the KSZ8863 is working as I can get port 1 and port 2 to transfer packets between each other, no issues at 100mbps just no packets to the processor. The schematic pdf I upload here shows my physical connections to the 407 and in the past I have successfully use the DP83848 out of the box. If anyone has a connection diagram to the 407 that works it would be much appreciated if you could share it along with any driver that you might have used.Update: I added a screenshot showing I do see rx data activity on the RII interface back at the processor.Thanks,

Hi, **Environment**- STM32F7xx LL Driver (STM32F7xx_HAL_Driver)- GCC arm-none-eabi 15.2 (also reproducible with GCC ≥ 12)- Compiler flag: `-fanalyzer`- File: `STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h`---**Problem**When building with `-fanalyzer`, GCC reports the following warning for several inline functions in stm32f7xx_ll_gpio.h:```warning: shift by count ('64') >= precision of type ('32')         [-Wanalyzer-shift-count-overflow]```**Root cause**`POSITION_VAL(VAL)` is defined as `__CLZ(__RBIT(VAL))`. When the analyzer considers `Pin = 0` as a possible runtime value (which it cannot rule out without additional constraints), then:- `__RBIT(0)` → `0`- `__CLZ(0)` → `32` (implementation-defined, GCC arm-none-eabi returns 32)- `32 * 2U` → `64` → shift of a `uint32_t` by 64 = **undefined behavior** per C11 §6.5.7The affected functions all follow the same pattern:// e.g. LL_GPIO_GetPinMode (line 307–311)return (uint32_t)(READ_BIT(GPIOx->MODER,    (GPIO_MODER_MODER0 << (POSIT