STM32 MCUs

Split from this thread  My firmware is based on this ccid usbd driver https://github.com/STMicroelectronics/stm32-mw-usb-device/blob/master/Class/CCID/Src/usbd_ccid.c . The issue that I face, the PC finishes receiving data immediately after receiving 256 bytes (10 bytes of header + 246 bytes of data). when I want to send to pc 253 bytes of data + 10 bytes of header (263 bytes in total) by splitting (64 bytes by 64 bytes) the PC finishes receiving data immediately after receiving the fourth chunk which is 256 bytes (10 bytes of header and 243 bytes of data), It doesn't wait for the fifth chunk, which carries the remaining 7 bytes of my data which arrives in an unknown message despite the fact that I define the size of the data to be sent as 253 bytes. Images 1 and 2 show these details captured by wireshark software.12 this is my code used to send data by chunks : uint8_t SC_Itf_XferBlock(uint8_t *ptrBlock, uint32_t blockLen, uint16_t expectedLen, USBD_CCID_BulkIn_DataTyp

Environment:- MCU: STM32H743IITx- USB PHY: USB3300 (ULPI, external HS PHY)- HAL version: STM32CubeH7 v1.11.6- Mode: USB Host, HS, ISOC transfer (UVC camera)- HFIR: 7500 (manually set for 60MHz PHY clock)Problem:HPRT.PENA is cleared by hardware at exactly HFNUM=16383 (14-bit framecounter maximum, about to roll over to 0). HPRT value at the moment ofHAL_HCD_PortDisabled_Callback: 0x00001409.Key observations:1. PCSTS=1 at the time of the event — device is still physically connected2. This happens 100% reproducibly at frame 16383, never at any other frame3. Without SDRAM (FMC) and LTDC active, the issue does not occur for 1.5+ hours4. With SDRAM only: occurs after ~7 minutes5. With SDRAM + LTDC (framebuffer in SDRAM): occurs within seconds6. Temporarily shorting USB3300 VCC to GND with a probe (adding bypasscapacitance) eliminated the issue for 50+ minutes — suggesting powersupply noise is a contributing factor, but the frame=16383 correlationis too precise to be purely noise-drivenQuestio

I am creating a commercial educational course for the STM32F103C8T6 microcontroller.My planned usage:Taking static screenshots of specific datasheet pages (register tables, timing diagrams, memory maps)NOT showing the entire datasheet — only essential pages (30-40 pages out of ~100)Narrating and explaining the content in my own wordsKeeping all STMicroelectronics logos and copyright notices visibleAdding my own annotations (arrows, circles, highlights)Providing links to ST's website for the full datasheetNOT redistributing the PDF fileMy questions:Is this allowed under ST's copyright policy for commercial educational content?Has ST ever taken action against any instructors for this type of usage?Do I need written permission from ST, or is this considered fair use?Example of similar usage (for reference):Hayducate learning website Thank you for your guidance.

Hi, is anybody able to confirm if the STM32H563ZIT3Q has an ethernet peripheral? Thanks, regards. 

Hi everyone, I’m building an open-source desktop IDE for microcontroller learning and prototyping, mainly focused on Arduino and STM32. The goal is not to replace professional tools like STM32CubeIDE, PlatformIO, Keil or IAR, but to provide a simpler learning-oriented workflow for students, technicians and training centers. Current / planned features: Arduino and STM32 project creation Build / upload workflow Serial monitor and serial plotter STM32 debug with GDB/OpenOCD Register / memory / stack views Basic SVD peripheral view Static analysis with cppcheck / MISRA-light Coverage reports Crash / HardFault reporting Power profiling demo via UART/SWO-style events QEMU/Renode simulation experiments I’m looking for honest feedback: Would such a tool be useful for education or training? Which feature would be most valuable? What would make you trust or not trust this kind of tool? Would it be better as a VS Code extension, standalone IDE, or educational toolkit? What pain points do you h

I've been struggling with a strange ADC problem for a while, and have now made some interesting observations.The scenarioI'm using an STM32G474, where HRTIM directly controls a peltier driver for temperature regulation. Temperatures are measured by ADC4 (12 bit resolution), running in DMA circular mode, triggered by TIM7, at 1 kHz. This works. Temperatures are coming in, and are being used for PID regulation.The problemQuite often – perhaps always – some of the temperature readings are being disturbed, but only at certain temperatures. At first, I thought that it was random noise, but in a graph the noise looks strange. Not random at all.After monitoring the raw ADC values that the DMA has thrown into memory, I discovered something that might be a clue – or it might just be a source of confusion. Every time a noisy sequence occurs, the ADC readout jumps to a lower nearby value where the five least significant bits are all 1, i.e. xxxx xxx1 1111. This is not random noise. It is if as th

Hello! I am encountering some issues when trying to run 2-Lane DSI with an STM32H747.Current Hardware Configuration:MCU: STM32H747 (using the Cortex-M7 core)Display Driver: Chipone CO5300 OLED Display DriverDisplay Panel: Round TOH143XRT-01CG2 1.43" 466×466 AMOLEDInterface: MIPI DSI (adapted command mode) Issue I am experiencing:I have successfully implemented 1-lane DSI communication between the STM32H747 and CO5300 display driver. However, when I configure both the STM32 DSI host and CO5300 for 2-lane operation, the display is not responsive (black screen / nothing being displayed) The display pipeline works as follows:DMA2D → Performs 2D graphics operations and copies framebuffer data to SRAMLTDC → Reads framebuffer from memory, performs layer blending, generates parallel RGB pixel stream (HSYNC, VSYNC, DE, pixel clock, RGB data)DSI Wrapper → Converts LTDC parallel RGB stream into a format suitable for DSI hostDSI Host → Packetizes pixel data into MIPI DSI packets, seriali

EVLSpin32G0B1 bord Program &Tools.

Hi,I have a DMA2D issue with a STM32N6 Nucleo-144 board. I can use the DMA2D to blend two framebuffers if the inputs are in the AXISRAM1. However, when one of the framebuffers is in AXISRAM3 (NPU RAM), the DMA2D doesn't copy from the relevant framebuffer. There is no error, but the output is invalid.I can copy to the AXISRAM3 using HPDMA without any issue. I have configured the RISAF4/5/6; otherwise, I am unable to copy to AXISRAM3. This is the code to configure RISAF4/5/6 (NPU RAMs): __HAL_RCC_RISAF_CLK_ENABLE(); RISAF4->REG[0].CFGR = 0x00000000; RISAF4->REG[1].CFGR = 0x00000000; RISAF4->REG[0].CIDCFGR = 0x000F000F; /* RW for everyone */ RISAF4->REG[0].ENDR = 0xFFFFFFFF; /* all-encompassing */ RISAF4->REG[0].CFGR = 0x00000101; /* enabled, secure, unprivileged for everyone */ RISAF4->REG[1].CIDCFGR = 0x00FF00FF; /* RW for everyone */ RISAF4->REG[1].ENDR = 0xFFFFFFFF; /* all-encompassing */ RISAF4->REG[1].CFGR = 0x00000001; /* enabled, non-secu

Hello, I am using a B-G431-ESC1 board to power some BLDC motors. I have alrady used it succesfully to spin some 2 pole pairs BLDC using Hall sensors for speed control. I even managed to implement some code to stop the motor at every half rotation of the shaft. It worked flawlessly with this type of motor. Now, I tried connecting a different type of BLDC, still 2 pole pairs but thats all I know since I don't have the datasheet. The motor profiling part went as expected and it managed to calculate all the relevant properties of the motor. I saved it and implemented the Hall sensors as aux speed control for Hall profiling. The difference from the other type of motor is that this one has a 6-wire Hall connection. Using an oscilloscope, I found that the extra cable was likely for temperature, so I left it unconnected. However, I keep getting Pin not connected on the pin wher the same cable is plugged (the blue cable). Whether I put the blue cable on H1, H2 or H3, the board doesnt recognize

Hi, On STM32F746G-DISCO board I have a problem with USART1 (ST-Link VCP): - TX (PA9) works fine – I can send messages- RX (PB7) doesn't receive any characters and I think the board is not waiting for commands Tested both polling (HAL_UART_Receive) and interrupt mode (HAL_UART_Receive_IT). Pins are configured correctly. Did anyone have similar issue on this board? Any ideas what can block RX? Thanks! /* USER CODE BEGIN 2 */ HAL_UART_Transmit(&huart1, (uint8_t*)"Connected\r\n", 11, 100); HAL_Delay(100); HAL_UART_Receive_IT(&huart1, &rxByte, 1); /* USER CODE END 2 *//* USER CODE BEGIN 4 */ void ProcessCommand(char *cmd); void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { if (huart->Instance == USART1) { if (rxByte == '\n' || rxByte == '\r') { if (rxIndex > 0) { rxBuffer[rxIndex] = '\0'; // zakończenie stringa ProcessCommand((char*)rxBuffer); rxIndex = 0; } } else { if (rxIndex < 15) // zabezpieczenie przed przepełnieniem { rxBuffer[rxI

We have a custom `STM32WL33CCV6` (`VFQFPN32`) board that should reach about `4 µA` in Deepstop, similar to the NUCLEO-WL33, but instead it drops only to roughly `450–500 µA` and appears to restart on Deepstop entry. `NRST` does not glitch low, and the behavior is unchanged with only `3.3V` and `GND` connected. We also tested direct `HAL_PWR_EnterDEEPSTOPMode()` with wake sources disabled, and it still appears to reboot rather than stay in Deepstop. We reviewed ST errata `ES0612` and applied the documented `VFQFPN32` workaround from section `2.2.9` for nonbonded GPIOs causing increased Run-mode current by forcing the listed nonbonded pins to pulldown at startup. That workaround had no effect on the Deepstop issue. The custom board’s `VFBSD / VLXSD / VDDSD / VDDRF` schematic and BOM appear close to the ST reference, so we are asking whether there are known WL33 low-power / SMPS / Deepstop pitfalls beyond errata `2.2.9` that could explain a persistent `~500 µA` floor or an apparent reset/

Hi all,I am trying to develop a bootloader software for STM32F765.I requires two features in it.1) jumping from Bootloader to Application2) jumping from Application to BootloaderI could make jump from Bootloader to Application very easily.But I am suffering with jumping from Application to Bootloader for 4-5 days now.The final code I tried is given below:void Bootloader_JumpToBootloader_Program(void) { void (*app_reset_handler)(void); __disable_irq(); SysTick->CTRL = 0 ; SysTick->LOAD = 0; SysTick->VAL = 0; HAL_RCC_DeInit(); HAL_DeInit(); /* 2) disable all enabled interrupts */ NVIC->ICER[ 0 ] = 0xFFFFFFFF ; NVIC->ICER[ 1 ] = 0xFFFFFFFF ; NVIC->ICER[ 2 ] = 0xFFFFFFFF ; NVIC->ICER[ 3 ] = 0xFFFFFFFF ; NVIC->ICER[ 4 ] = 0xFFFFFFFF ; NVIC->ICER[ 5 ] = 0xFFFFFFFF ; NVIC->ICER[ 6 ] = 0xFFFFFFFF ; NVIC->ICER[ 7 ] = 0xFFFFFFFF ; NVIC->ICPR[ 0 ] = 0xFFFFFFFF ; NVIC->ICPR[ 1 ] = 0xFFFFFFFF ; NVIC->ICPR[ 2 ] = 0xFFFFFFFF ; NVIC->ICPR[ 3 ]

Hi  i have a board with STM32F4 and an EMMC. And I am using FATFS.  I managed to enable the STM32 RTC and added the necessary code in get_fattime(); There is one problem stil: under windows "created" and "modified" date are shown corerctly. But "accessed" date is wrong.  See attached image.  Any clue what is going wrong? Thx  

Dear all,I think I have discovered a bug in the CMSIS headers supplied for the STM32H7RSx and STM32H7x MCUs.In "Drivers/CMSIS/Device/ST/STM32H7RSxx/Include/stm32h7rsxx.h", there are definitions for ATOMIC_SET_BIT() and ATOMIC_CLEAR_BIT() among others, see https://github.com/STMicroelectronics/cmsis-device-h7rs/blob/7e6e213ddc397c76622a0aca2f623ccc3b34c010/Include/stm32h7rsxx.h#L162:/* Use of CMSIS compiler intrinsics for register exclusive access */ /* Atomic 32-bit register access macro to set one or several bits */ #define ATOMIC_SET_BIT(REG, BIT) \ do { \ uint32_t val; \ do { \ val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ } while(0)and the "register" in the description and the '__IO' qualifier in the code hint that this can be used for peripheral registers. This suspicion is correct, e.g., see https://github.com/STMicroelectronics/stm32h7rsxx-hal-driver/blob/1bde483bc7ab4883c2ef643e5a16ad6b303a631f/S

I'm writing firmware for a development board based on the STM32H743 MCU, and I want to use an external GPIO input as the trigger or synchronization signal of DMAMUX to initiate DMA transactions. However, it seems that very little information is available on using GPIOs to start DMAs. In the reference manual, "Table 127. DMAMUX2: assignment of trigger inputs to resources" and "Table 128. DMAMUX2: assignment of synchronization inputs to resources", it shows two trigger input signals: "Syscfg_exti0_mux" (number 20), and "Syscfg_exti2_mux" (number 21). So it seems to suggest that the EXTI trigger sources can indeed be used to trigger the DMA, but these two signals are not mentioned anywhere in the entire reference manual, there's no block diagram showing exactly what GPIO pins are connected. It says "SYSCFG" and "MUX", so they're probably the outputs controlled by programming SYSCFG_EXTICR1, SYSCFG_EXTICR2, SYSCFG_EXTICR3, SYSCFG_EXTICR4. But there are 4 EXTICRx and only two "exti_sys

I am currently working with the LoRa-E5 Mini module based on the STM32WLE5JC microcontroller, and I am using STM32CubeIDE version 2.1.0 for development. I have successfully tested basic GPIO functionality (LED blinking), and I am now trying to implement LoRa-based communication (transmission and reception) using the integrated SubGHz radio. However, I am facing challenges in properly configuring and utilizing the SubGHz_Phy middleware and radio drivers within STM32CubeIDE. Specifically, I need guidance on the following: The correct procedure to enable and configure the SubGHz radio peripheral in STM32CubeIDE for STM32WLE5JC. How to properly include and use the SubGHz_Phy middleware for basic LoRa communication. Availability of any official example projects (such as Ping-Pong or Tx/Rx) compatible with STM32CubeIDE 2.1.0 for the LoRa-E5 Mini module. Proper configuration of radio parameters (frequency, spreading factor, bandwidth) for reliable communication. Any recommended steps to ensu

Board / SoCBoard: NUCLEO-WB09KESoC: STM32WB09SoftwareZephyr version: v4.4.0-rc2-41-g149c8b1758a8Toolchain / build system: West + Zephyr standard build flowIssue summaryWhen building a very small Zephyr application for NUCLEO-WB09KE, simply enabling:CONFIG_BT=ycan cause intermittent boot failure.The failure happens very early in boot:no UART outputno boot bannerno application printk()main() appears to never run in failed bootsThis happens even when the application does not call any Bluetooth API.Minimal applicationmain.c#include <zephyr/kernel.h> #include <zephyr/sys/printk.h> int main(void) { while (1) { printk("M\n"); k_busy_wait(100000); } return 0; }Minimal project configurationprj.confCONFIG_BT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_EARLY_CONSOLE=y CONFIG_PRINTK=y CONFIG_ASSERT=y CONFIG_ASSERT_VERBOSE=y CONFIG_LOG=n CONFIG_PM=nObserved behaviorWith Bluetooth disabled, the board boots and repeatedly prints:M M M ...With CONFIG_BT=y enabled, boot becomes

Hi, I need to measure a 4.2V battery while my MCU's supply varies between 2.0V and 3.3V. Since VDDA is the ADC reference, raw ADC counts will drift as the supply changes. Is this the correct method? My plan: Feed the battery voltage through a 10K/7K5 divider into one ADC channel (scaled to stay below VDDA_min = 2.0V). Read VREFINT on a second ADC channel. Use VREFINT (whose true value is known from the factory calibration in system memory) to back-calculate the actual VDDA, then convert the battery channel's raw count into volts. The formula being:V_battery = 3.0 V × (VREFINT_CAL / VREFINT_DATA) × (ADC_battery / 4095) × ((R1 + R2) / R2)   Is this the correct approach for getting a supply-independent battery reading on this part? Anything I'm missing... sampling time for VREFINT, divider impedance vs. ADC sample-and-hold, or calibration register quirks specific to the C0 series?   Thank you

Hi! I'm trying to design a project that will use an stm32u5, and I would like to add PSRAM to it. Most higher-capacity PSRAMs seem to want to run at 1.8V rather than 3.3V, from what I can tell.  The particular U5 I've tentatively selected (the U595), has a VDDIO2 power pin, which I understand that I can run at 1.8V while running the rest of the MCU at 3.3V. This feature seems specifically designed to address this use case (and Claude and Gemini insist that it's possible with the right u5 variant, though I'm well aware how confidently wrong AI tools can be). The datasheet says that VDDIO2 affects Pin Bank G. However, I can't quite seem to figure out how I might actually connect to a PSRAM chip exclusively with this bank.  I haven't been in these waters before, so it's possible I'm overlooking something straightforward - a lot of the configuration options for PSRAM are new to me. It seems I could use FMC or SPI to connect to the PSRAM chip, but playing around in cubeMX with all

In the code examples provided with AN4502, this pattern is used often:  while ( STACK_SMBUS_IsReady(pcontext) != SMBUS_SMS_READY) { } But in our code, when built with the Release CMake preset, this hangs forever.My understanding is that this is because the `StateMachine` member of the SMBus context struct (SMBUS_StackHandleTypeDef) is getting updated by the SMBUS interrupt handlers, but it isn't marked volatile:  * @brief Stack state machine handling structure - the stack operation context */ typedef struct { uint32_t StateMachine; /*!< Keeps track of current stack state */ SMBUS_HandleTypeDef *Device; /*!< HAL driver handle */ uint8_t *ARP_UDID; /*!< A UDID used in ARP */ st_command_t *CurrentCommand; /*!< NULL, unless a command is being processed */ st_command_t *CMD_table; /*!< Pointer to first record in the table of all supported commands */ uint32_t CMD_tableSize; /*!< The supported commands table size */ #ifdef PMBUS13 SMBUS_ZoneStateTyp

Hi, I would like to use MDMA to get values from ADC. I have one adc set with 6 channels, starting conversion with timer (100µs). So I would like to save in memory adc values like that : val1, val2, val3, val4, val5, val6 -> val1(100µs),val1(200µs)...val1(1000µs),val2(100µs),val2(200µs)...val2(1000µs)...val6(1000µs) the destination memory is 60 values of 16 bits. That means I would like to be interrupted every 1ms by MDMA. So I use this configuration (at beginning I would like to test only 2 first values val1 and val2): this is the code to initialize MDMA MDMA_HandleTypeDef hmdma_mdma_channel0_dma1_stream2_tc_0; MDMA_LinkNodeTypeDef node_mdma_channel0_dma1_stream2_tc_1; /** * Enable MDMA controller clock * Configure MDMA for global transfers * hmdma_mdma_channel0_dma1_stream2_tc_0 * node_mdma_channel0_dma1_stream2_tc_1 */ void MX_MDMA_Init(void) { /* MDMA controller clock enable */ __HAL_RCC_MDMA_CLK_ENABLE(); /* Local variables */ MDMA_LinkNodeConfTypeDef nodeConfig; /*

I'm using an STM32G431 with FreeRTOS. I have a total of 5 tasks, including the default task, and all of them were set to osPriorityLow. With this configuration, the tasks did not run properly. When creating the tasks, NULL was not returned and no error occurred. After changing all task priorities to osPriorityNormal, the problem was fixed. I don't really understand why this happens. Each task has a reasonable osDelay(), so I don't think any specific task is blocking the others. Also, if a task were blocking, I would expect the same problem to happen even after changing the priority. I also tried changing the heap size and the stack size, but that did not seem to be the cause. Has anyone experienced a similar issue, or does anyone know why changing all tasks from osPriorityLow to osPriorityNormal would make a difference?    

MCU STM32H503KBU internal clock  64 MHz   During a UART restart,the HAL_UART_Init function callsHAL_RCCEx_PeriphCLKConfig, which results in a HardFault_Handler   void UART_Set_BaudRate(UART_HandleTypeDef *huart, uint32_t BaudRate) { if (HAL_UART_DeInit(huart)!= HAL_OK) { Error_Handler(); } huart->Instance = USART1; huart->Init.BaudRate = BaudRate; huart->Init.WordLength = UART_WORDLENGTH_8B; huart->Init.StopBits = UART_STOPBITS_1; huart->Init.Parity = UART_PARITY_NONE; huart->Init.Mode = UART_MODE_TX_RX; huart->Init.HwFlowCtl = UART_HWCONTROL_NONE; huart->Init.OverSampling = UART_OVERSAMPLING_16; huart->Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; huart->Init.ClockPrescaler = UART_PRESCALER_DIV1; huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; if (HAL_UART_Init(huart) != HAL_OK) { Error_Handler(); } if (HAL_UART_Receive_IT( OW.huart, &uart_temp, 1) != HAL_OK) Error_Handler(); }   If y

Hi everyone,I am experiencing a very specific initialization issue with a custom board based on the STM32WB55RGV6.We recently manufactured a batch of 30 boards. 22 of them are working flawlessly, but 8 boards fail to start the BLE radio on a cold boot (Power-On Reset). They all run the exact same firmware and have the exact same layout.Hardware details:MCU: STM32WB55RGV6HSE: 32 MHz crystal (CS06410-32M)LSE: 32.768 kHz crystalRF: MLPF-WB55-01E3 filter + Ceramic AntennaSymptoms & Debugging Steps Taken:No RF Output: Using an SDR and Near Field Probes, I confirmed there is zero RF energy being transmitted on the 2.4 GHz band during a cold boot on the faulty boards.HSE is Alive: I probed the 32 MHz HSE crystal with an oscilloscope, and it is oscillating perfectly at 32.000 MHz.The FUS Workaround (The Clue): If I send an AT#FUS command via UART to enter the Firmware Upgrade Services mode, the CPU2 wakes up and the board successfully advertises the "STM_OTA" network.Warm Boot Success: If