STM32 MCUs

Hello,i have configured timer1 to trigger via CC1  an  adc + dma.For the DMA i have  placed the TC irq routine and placed a gpio toggle to follow with a logic analyzer like shown below void DMA2_Stream0_IRQHandler(void){ if (DMA_GetITStatus(DMA2_Stream0, DMA_IT_TCIF0) != RESET) { GPIO_ResetBits(gpio_led_port,gpio_led2); GPIO_SetBits(gpio_led_port,gpio_led2); GPIO_ResetBits(gpio_led_port,gpio_led2); DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF0); } }And this is my nvic setup  SysTick_Config(SystemCoreClock / 1000); NVIC_InitTypeDef NVIC_InitStructure; NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0); NVIC_InitStructure.NVIC_IRQChannel = SysTick_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); NVIC_InitStructure.NVIC_IRQChannel = DMA2_Stream0_IRQn; NVIC_InitStructure.NVIC_IRQChan

Hello @STTwo-32,I was having the same issue and pressing the "start wireless stack" button did the trick for me. I was assuming after flashing the FUS & BLE Stack firmware, is that the CPU2 would be up and running already. So, does this mean that we need to manually start the CPU2 by pressing the button? Thanks!This post is created based on a comment for this post.

Hi All,I'm struggling to get LPTIM1 to wake from STOP mode on the STM32U5 series parts. I have a STM32U575ZI Nucleo board. When I use SLEEP mode, the LPTIM1_IRQHandler in stem32u5xx_it.c is hit. When I use STOP mode, it is not. I made an example with CubeMx to make it as simple as possible. I'll attach the CubeMx ioc and main.c, but see below for the snippit with all the CubeMx comments removed. Presumably its not an issue with the LPBAM, as if I set the RCC->SRDAMR to all ones, it still fails.Any ideas?ThanksJeff int main(void){HAL_Init();SystemClock_Config();MX_LPTIM1_Init();__HAL_RCC_LPTIM1_CLKAM_ENABLE();HAL_LPTIM_Counter_Start_IT(&hlptim1);while (1){HAL_SuspendTick();HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); // Doesn't work//???HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); // WorksHAL_ResumeTick();}}

Hello world :)I found STLINK-V3MODS extremely useful for automation testing (NuttX RTOS). I have ~50 different boards, some of them does not have on-board flashing capability, thus either JTAG/SWD or UART needs to be used.Most of the boards that use UART based BootROM need external Reset and Boot pins control. These are achieved by RTS and DTR output lines of USB-to-UART converters (i.e. CP2101, PL2303, FTDIx232, CH3xx, etc).I discovered that STLINK-V3MODS can have second UART port enabled by flashing firmware and selecting proper configuration. Both UARTs show up as separate serial port devices (i.e. /dev/cuaU0 and /dev/cuaU1 on FreeBSD). That gives two UARTS + JTAG/SWD over single USB connection, potentially serving 3 different boards under test. But VCP has no control lines, and Bridge UART has RTS/CTS (output/input) not RTS/DTR (output/output). That decreases possible use cases from 3 to 1 (SWD+VCP to automate testing of single board).My question is would it be possible to add new

HiI created a composite USB device with CDC and UVC classes using usbd. The device is detected, camera image streaming works, and data transfer via CDC (virtual serial port) also works. However, after a random time, communication on the CDC data out endpoint stops. Reopening this endpoint solves the problem. The same thing happens with EP0. When I repeatedly open and close the serial port, EP0 stops receiving data after some time. If I stop video streaming, CDC communication is stable.Sometimes I also get an incorrect video frame when data is transmitted via CDC. I'm using FreeRTOS, but running everything in a single thread didn't solve the problem. I have no further ideas what could be wrong.Any ideas?Artur

I am using two NUCLEO-U385RG-Q boards for I3C communication — one configured as the Controller (Master) and the other as the Target (Slave). I am trying to implement an IBI event with Pending Read Notification, and would like to know whether it is possible to perform Repeated START between the IBI and the subsequent Private Read? The transfer format for Pending Read Notification can be referenced in the following document, specifically Figure 6 – MCTP over I3C packet transfer format: I3C Target to I3C Controller:Management Component Transport Protocol (MCTP) I3C Transport Binding Specification  From the transfer format, it can be seen that Pending Read Notification essentially means that after the Controller receives an IBI event, it then performs a Private Read to the corresponding Target.Between these two operations, either STOP + START or Repeated START can be used. With the current SDK, STOP/START sequence between IBI and Private Read is possible (i.e., the Cont

Hello!I have an STM32WB5MMG with a breakout board (more specifically Sparkfun ATP breakoutSparkFun MicroMod ATP Carrier Board - DEV-16885 - SparkFun Electronicswith the STM32WB5MMG module SparkFun MicroMod STM32WB5MMG Processor - DEV-21438 - SparkFun Electronics)So, it is not in a nucleo version. I am trying to see if I can just see the BLE device on my phone with the "ST BLE Sensor" app (or "ST BLE Toolbox") app.I downloaded the STM32WB packages on githubSTMicroelectronics/STM32CubeWB: Full Firmware Package for the STM32WB series: HAL+LL drivers, CMSIS, BSP, MW, plus a set of Projects (examples and demos) running on all boards provided by ST (Nucleo, Evaluation and Discovery Kits). (github.com)The STM32WB5MM-DK is basically what I have but just in a different format, so I try and follow the examples for that board.In the github download, I opened this example project:STM32CubeWB-master\Projects\STM32WB5MM-DK\Applications\BLE\BLE_p2pServer\And then started to follow the readm

Hi everyone! I have a working project based on STM32F746 with LCD, Ethernet and SDRAM(IS42S16160J-6TL) and now we are moving it to STM32H753II. I set up a FMC controller and tested whole SDRAM region with 8, 16, and 32 bit access. I use GCC. During this migration I discovered a line of the code that always generate a HardFault error with UNALIGNED flag set. This is this line: if (strncmp(data + i, boundary_str, 9) == 0) from: for (i = 0; i < len; i++) { if (strncmp(data + i, boundary_str, 9) == 0) { boundaryOffset = i + 9; break; } } data is placed in SDRAM like this: char eth_rx_buf[MAX_LENGH] __attribute__((section (".sdram_noncached"))); and boundary_str like this: static const char boundary_str[10] = "boundary="; HardFault happens every time when i becomes 10. MPU settings were copied from STM32F7 project: /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; MPU_InitStruct.BaseAddress = 0xC0000000; MPU_I

Hello everyone, I am working with an STM32H753ZI board and I want to set up CAN communication. I’m a bit confused about what changes I need to make. Here are my main questions: Does the STM32H753ZI use the regular CAN peripheral or the newer FDCAN peripheral? In CubeMX, which settings (baud rate, prescaler, seg1, seg2, etc.) are recommended for 500 kbps? Since the H753ZI board doesn’t have an onboard CAN transceiver, which external transceiver IC (e.g., MCP2551, SN65HVD230, TJA1050, etc.) would be best to use with it? Are there any example CubeIDE projects or reference codes specifically for CAN/FDCAN on the STM32H7 series? How to setup the pinout  configuration and clock configuration. I want to make sure I configure the peripheral and wiring correctly before testing. Any guidance, example code, or links to reference materials would be greatly appreciated. Thanks in advance!

Hi everyone , I'm testing ultra-low power on the NUCLEO-WL55JC using STM32CubeIDE . My goal is to reach ~0.9 µA in Stop 2 mode, but I consistently measure around 2.9 mA, even with the debugger disconnected. My setup: Stop 2 mode enabled MSI @ 100 kHz, PLL disabled PVD disabled All unused GPIOs set to analog SUBGHZSPI clock disabled Debug disabled CPU2 not activated Tick suspended Entering Stop 2 with HAL_PWREx_EnterSTOP2Mode() Measurement: JP7 and JP8 removed Powered via JP1 using STLINK-V3PWR Measured with STM32CubeMonitor-Power Question: Why is the current still so high? Is there anything specific on the NUCLEO-WL55JC board (RF switch, etc.) that needs to be disabled? Any working CubeIDE example that reaches ~0.9 µA?

Hello,I am having an issue with my STM32WBA65MI-based project file (IOC file) and CubeMX (6.15.0). It also happens when configuring the IOC file in CubeIDE 1.19.0.When I configure the clocks and then generate code and save the IOC file and then close the IOC file, the code is correctly generated. However, when I open the IOC file again, the clock settings are different:Cortex Clock Selection MuxCPU System Timer shows as LSE, despite previously having saved and generated as HCLK1 / 8. This means the CPU System Timer runs at 0.032768MHz rather than 12MHz.System Clock MuxThe System Clock Mux shows as HSE, despite previously having saved and generated as PLLCLK. This sets the SYSCLK to 32MHz (and has consequences downstream for peripherals)Related to the System Clock Mux, the HPRE5 Prescaler gets reset from / 4 (which I had saved) to / 1.If I were to generate code, it would replace the "correct" code with the new settings.Double-checking the original generated code, it seems that the setti

Hello,I’m using the STM32L475VGT6 board and need drivers for the MAX30102/MAX30100 and Protocentral MAX86150 sensors. I couldn’t find official or compatible drivers for these sensors on this MCU.If anyone has links to drivers, example code, or advice on integration with STM32L475VGT6 (using STM32CubeIDE or HAL libraries), please share.Thanks in advance!

  Hello, I am working with an NUCLEO-H753ZI (ADC1/ADC2 with DMA1/DMA2, and ADC3 with BDMA).My goal is to store ADC conversion results directly into a uint32_t buffer using DMA, so that the 16 valid bits from the ADC are automatically zero-extended to 32 bits in memory. The reference manual describes the possible data widths (byte, half-word, word) for peripheral and memory sides, but I could not find a clear statement about what happens when: Peripheral data alignment = half-word (16 bits) Memory data alignment = word (32 bits) Does the STM32H7 DMA (DMA1/DMA2 and BDMA) guarantee that the upper 16 bits are always zeroed when transferring 16-bit peripheral data into 32-bit memory? Or are the upper bits undefined? In CubeMX, when configuring ADC1 or ADC2 with DMA, it is not possible to set MemDataAlignment=WORD in the .ioc file (the tool only allows HALFWORD). Is this a CubeMX limitation, or does it reflect a real hardware restriction? Thanks in advance for

Akkording to AN3155, July 2025: "The highest tested baud rate (BHigh) is 115200." Have tried with 921600 and that seems to work fine.  Is the recommodation from ST that not use above 115200?

HiI modified nBOOT_SEL Bit, but still the PA14-BOOT0 Pin level has no effect. The CPU starts always on in Main flash memory. I have these 2 situations (RM0490 Rev 5 page 53) If PA14 is low level: Main flash starts. This is okIf PA14 has high level: System memory (Internal Bootloader) should start. This is not working. Always application on flash memory starts.This is the Flash_OPTR content: This is the board schematic: J13 is JTAG: this is workingJ12 is access to serial USART loader. RX and TX is connected to PA9/PA10.J12 serial loader is working in case flash is empty. This is the routine for modify the Option Byte: HAL_StatusTypeDef ClearnBootSel() { FLASH_OBProgramInitTypeDef OB; HAL_FLASHEx_OBGetConfig(&OB); /* OB.USERConfig returns the FLASH_OPTR register */ // Use it to check if OB programming is necessary if (OB.USERConfig & FLASH_OPTR_nBOOT_SEL) { HAL_FLASH_Unlock(); HAL_FLASH_OB_Unlock(); OB.OptionType = OPTIONBYTE_USER; OB.USERType = OB_USER_NBOOT_SEL

Hello,I am looking for a solution to a problem. To put it briefly, I want to update the program of a microcontroller via a USB key. It is an STM32L4+ series microcontroller.I saw on an STM32F429I-DISC test board that there was documentation for updating via USB flash drive. (https://www.st.com/resource/en/application_note/an3990-upgrading-stm32f4discovery-board-firmware-using-a-usb-key-stmicroelectronics.pdf)Since this is not the same microcontroller as the one I am targeting, I was wondering if this is possible with the STM32L4+. Thank you in advance for your response.

hi,The PCB with STM32F746zgtx has already been shipped to the customer.Pin PA12 is responsible for controlling the RS485 DIR.The documentation states that Pin PA12 is powered by the Vddusb pin.It turns out that pin PA12 doesn't drive the high voltage (3.3V) because the Vddusb pin isn't connected.I can't make any hardware changes. Is there any way to force this in software?I've tried unsuccessfully:1. Set Open Collector + Pullup,2. Set Push-Pull,3. Set PIN PA11 (which is also powered by Vddusb) as a PULL-UP input, hoping it will transfer to PA12.4. Pin PB14 controls the LED (via ground). This pin also receives a high signal from the Vddusb pin, so I thought it might be possible to transfer the high signal from the LED to pin PA12, but it didn't work.5. I tried setting PA12 as hardware control (RS485).Do you have any ideas?  

Hallo,does exist, in FileX, a function that returns the free available space not yet utilized?Thank you.

Specifically the SNB (SSN1 & SSN2 in the data sheet) bits are defined erroneously as being 3 bits wide at position 6, whereas it should be 7 bits wide, allowing all 128 sectors in each bank to be erased.#define FLASH_CR_SNB_Pos (6U) #define FLASH_CR_SNB_Msk (0x7FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ #define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ #define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ #define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */This causes the HAL_FLASHEx_Erase to behave

The new STM32L4R9 svd file (version 2.0) has renamedTIM1_OR2 to TIM1_AF1,TIM1_OR3 to TIM1_AF2Removed TIM1_OR1 which is in the reference manual containing ETR_ADC1_RMP and TI_RMPAdded a new TIM1_TISEL at offset 0x68 which is not in the current reference manual.Is a new reference manual due and/or are these changes correct?p.s. Thank you for fixing many of my previously reported issues and adding a lot of useful descriptions.Regards, Kc

Greetings,This is my frist time with wireless mcu. I just want to ask whether RTC is required for LORA Sub GHz Phy communication ? Any help will be greatful.

Hello,I'm having trouble building a LoRaWAN project targeting the STM32WLE5JCI6. The same error occurs even on a clean, newly created project, which leads me to believe there might be a compatibility issue between the IDE and the software package.■ The error I'm facing:../Middlewares/Third_Party/LoRaWAN/Mac/LoRaMac.c: In function 'ProcessRadioRxDone': ../Middlewares/Third_Party/LoRaWAN/Mac/LoRaMac.c:1650:40: error: 'McpsIndication_t' {aka 'struct sMcpsIndication'} has no member named 'ResponseTimeout'This error indicates that LoRaMac.c is trying to access the ResponseTimeout member of the McpsIndication_t struct, but the corresponding LoRaMac.h file lacks that definition.■ My setup:Target MCU: STM32WLE5JCI6STM32CubeIDE Version: 1.19.1 (Clean install from the official website)STM32CubeWL Package: Latest version (Installed via the IDE's package manager)■ Steps I have already taken:Cleanly reinstalled both STM32CubeIDE and the STM32CubeWL package.Deleted the old project and workspace, the

Hello everyone!I have just noticed that The OPAMP_CSR_OPARANGE bit in NUCLEO-U575ZI-Q is not shown during debug mode. Some bug perhaps?..

Hello everyone,I am facing a strange behavior when using ADC scan + DMA with an STM32L476RG.To debug the issue, I created a very simple test code: the MCU performs a scan measurement on 4 channels of ADC1 (PC0, PC1, PC2, and PC3) using DMA.Test setup:ADC1 configured in scan modeDMA transfer to conversions[4] bufferChannels: PC0, PC1, PC2, PC3Observation:On a Nucleo-L476RG (MB1136 C-04), the code works as expected. Each channel returns a value of around ~550 in all positions of conversions[4].On my custom hardware, running the exact same firmware, I see a very different behavior:conversions[0] shows a value around ~2200conversions[1], [2], and [3] remain stuck at 0This issue happens only on my custom board.I have already checked the supply pins:VDD, VDDA, VREF+ → all are properly connected and supplied with ~3.3VGND and VSSA are also properly tiedI will attach the relevant section of my schematic showing the MCU connections.Has anyone faced a similar issue or has suggestions on what cou

I have a project working on the NUCLEO-N657X0-Q with FSBL and an application. In total I am using under 1MB of the 64MB flash this board has. I was wondering if it was possible to segment off the rest of the flash to be used as a mass storage device over USBX with FileX. I am using the load and run config instead of XIP. The current flash usage is as follows: 0x70000000 - FSBL (66KB) 0x70100000 - Application (100KB) 0x71000000 - Weights and activations (400KB) I know I can use cube programmer to write external data directly to the memory mapped flash drive but I would prefer to use standard file access tools. I have successfully implemented mass storage on a STM32H5 but that MCU didn't need to also load firmware so FileX could manage the whole drive as if it was empty.  Alternatively would it be possible to instead use FileX to load the FSBL/Application parts instead of the external memory manager?