in RM0316 rev.8. FLASH_ACR.HLFCYA is described as enabling Flash half cycle access. Narrative in chapter 4.2.2 says:
If there is not any high frequency clock available in the system, Flash memory accesses can
be made on a half cycle of HCLK (AHB clock).
Besides a subsequent sentence which prohibits using half-cycle mode when AHB divider is non-1, I can't find any other reference to this mode, not in RM0316, not in DS, nowhere else.
Can please ST quantify "high frequency clock" in the quote above, and also explain/quantify what are the benefits of using this mode.
Thanks,
JW
