DSI Clock Frequency

[DPfei.16]

Hello,

i have 25 MHz HSE Clock.

The DSI PLL settings are as follows: IDF 5, NDIV 80, ODF2

With these settings i measure an DSI clock of 100 MHz on the DSI_CKP pin.

But Cube says that the DSI clock is 200 MHz.

I use a STM32F769NI device with 2 DSI data lanes.

Do you have any idea?

BR

Daniel

[Tesla DeLorean]

They do on the surface look like appropriate numbers for a 200 MHz pixel clock.

As I recall the DSI clocks on both edges, effectively doubling the bandwidth, ie 100 MHz clock on pin equates to 200 Mbps on the wire.

I built a decoder for the LTDC/DSI clocks, will have to dig that up.

[DPfei.16]

Hi Clive,

thank you for your response!

I know DSI uses double data rate (DDR) and therefore data is transfered on the rising and the falling clock edge. This means when I have a DSI clock frequency of 200 MHz I have a bandwitdth of 400 Mbit/sec.

But I don't understand why the measured DSI clock frequency is only the half of the calculated DSI clock frequency.

[Tesla DeLorean]

The STM32's unit clocks at 200 MHz internally so it can generate data on both edges of the 100 MHz clock on the wire.

[Tesla DeLorean]

void plldecode(void) // sourcer32@gmail.com
{
  uint32_t vcoinput, vco;
  uint32_t oscsource;
  uint32_t pllcfgr = RCC->PLLCFGR;
  uint32_t plli2scfgr = RCC->PLLI2SCFGR;
  uint32_t pllsaicfgr = RCC->PLLSAICFGR;
  uint32_t pllp, pllq, pllr;
  uint32_t p, q, r;
 
  /* Configure the PLLSAI division factor */
  /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
  if((pllcfgr & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
    oscsource = HSI_VALUE; /* In Case the PLL Source is HSI (Internal Clock) */
  else
    oscsource = HSE_VALUE; /* In Case the PLL Source is HSE (External Clock) */
 
  vcoinput = (oscsource / (uint32_t)(pllcfgr & RCC_PLLCFGR_PLLM));
 
 
  vco = (vcoinput * ((pllcfgr & RCC_PLLCFGR_PLLN) >> 6));
 
  pllp = (((pllcfgr & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
  if (pllp) p = vco / pllp; else p = 0;
 
  pllq = (pllcfgr & RCC_PLLCFGR_PLLQ) >> 24;
  if (pllq) q = vco / pllq; else q = 0;
 
  pllr = (pllcfgr & RCC_PLLCFGR_PLLR) >> 28;
  if (pllr) r = vco / pllr; else r = 0;
 
  printf("PLL    P:%9d Q:%9d R:%9d\n", p, q, r);
 
 
  vco = (vcoinput * ((plli2scfgr & RCC_PLLI2SCFGR_PLLI2SN) >> 6));
 
  pllp = (((plli2scfgr & RCC_PLLI2SCFGR_PLLI2SP) >> 16) + 1) * 2;
  if (pllp) p = vco / pllp; else p = 0;
 
  pllq = (plli2scfgr & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
  if (pllq) q = vco / pllq; else q = 0;
 
  pllr = (plli2scfgr & RCC_PLLI2SCFGR_PLLI2SR) >> 28;
  if (pllr) r = vco / pllr; else r = 0;
 
  printf("PLLI2S P:%9d Q:%9d R:%9d\n", p, q, r);
 
 
  vco = (vcoinput * ((pllsaicfgr & RCC_PLLSAICFGR_PLLSAIN) >> 6));
 
  pllp = (((pllsaicfgr & RCC_PLLSAICFGR_PLLSAIP) >> 16) + 1) * 2;
  if (pllp) p = vco / pllp; else p = 0;
 
  pllq = (pllsaicfgr & RCC_PLLSAICFGR_PLLSAIQ) >> 24; // 2..15
  if (pllq) q = vco / pllq; else q = 0;
 
  pllr = (pllsaicfgr & RCC_PLLSAICFGR_PLLSAIR) >> 28; // 2..7
  if (pllr) r = vco / pllr; else r = 0;
 
  printf("PLLSAI P:%9d Q:%9d R:%9d\n", p, q, r);
 
  {
    uint32_t dckcfgr1 = RCC->DCKCFGR1;
    uint32_t divr = 2 << ((dckcfgr1 & RCC_DCKCFGR1_PLLSAIDIVR) >> 16); // 2,4,8,16
    uint32_t lcdclk = r / divr;
    printf("LCDCLK   %9d, %6.2lf MHz\n", lcdclk, (double)lcdclk*1e-6);
  }
 
  {
    uint32_t dsiwrpcr = DSI->WRPCR;
    if (dsiwrpcr & 1) // Enabled
    {
      uint32_t odf = 1 << ((dsiwrpcr >> 16) & 0x0F); // 1,2,4,8
      uint32_t idf = ((dsiwrpcr >> 11) & 0x07);
      uint32_t ndir = ((dsiwrpcr >> 2) & 0x7F); // 10..124
      uint32_t dsi = (HSE_VALUE * ndir) / (idf * odf);
      printf("DSIPLL   %9d, %6.2lf MHz\n", dsi, (double)dsi*1e-6);
      printf("lbClk    %9.3lf KHz\n", (double)dsi / 8000.0);
      printf("TXEscape %lf\n", (double)dsi / (8000.0 * 15620.0));
    }
  }
}

[DPfei.16]

Hi Clive,

many thanks for your help!

BR

Daniel