SPI on STM32G071 not behaving as expected

[Barber.Mark]

Hi,

i have  new design that i am migrating to the STM32G071 and having issues with the SPI1 port PB3,PB4,PB5. 

Changing CPOL and or CPHA during init code do not seem to have any impact, when powered down and restarted.

I am seeing 9 clock pulses when set to 8 bit data. Suspect this might be issues with the overall SPI setup.

the init code is simple changed to the absolute simplest format.

ignoring setting the PB3,4,5 GPIO pins as they are good i can see the signals on the cro

// bidirectional mode full 2 line

SPI1->CR1&=~SPI_CR1_BIDIMODE;

// set as master

SPI1->CR1|=SPI_CR1_MSTR;

// CPOL clock idle low

SPI1->CR1&=~SPI_CR1_CPOL;

// CPHA rising clock edge

SPI1->CR1&=~SPI_CR1_CPHA;

// set LSBFIRST low we send MSB first

SPI1->CR1&=~SPI_CR1_LSBFIRST;

// set up SSM pin

SPI1->CR1&=~SPI_CR1_SSM;

SPI1->CR1&=~SPI_CR1_SSI;

// configure data size 8 bits

SPI1->CR2|=(SPI_CR2_DS_2|SPI_CR2_DS_1|SPI_CR2_DS_0);

// set the reception threshold

SPI1->CR2|=SPI_CR2_FRXTH;

// set TI mode

SPI1->CR2|=SPI_CR2_FRF;

// DISABLE ssoe OUTPUT

SPI1->CR2&=~SPI_CR2_SSOE;

// enable SPI port

SPI1->CR1|=SPI_CR1_SPE;

The attached cro screen shot shows blue is the CS chip select, red is the clock 9 pulses,

and green is MOSI sending 0x55 as a test.

looking at the MOSI/CLK i am sending 001010101

This one has me stumped.

Mark

[TDK · Accepted solution]

> // set TI mode

> SPI1->CR2|=SPI_CR2_FRF;

TI mode locks CPOL = CPHA = 1 regardless of settings in CR1.

It's also only really usable with hardware NSS because of the extra pulse. Hence you see 9 clocks instead of 8. One of these is with NSS high.

Sounds like you want normal Motorola mode, not TI mode.

[Barber.Mark]

Perfect thank you. that solved my issues.