Using TIM1 for get two positive pulses.

One possible implementation is to use a one shot timer who can use dma to update the channel 2 output compare/toggle. Here just need 2 compare values in cyclical form. The timer only needs to last say 100us and wait for retrigger a second later, by software or from a signal.

Another way maybe to combine 2 timers onr controller by the other.

Thank you for answer.

Will test work DMA with TIM.

Normally, you can't output shifted PWM pulses with arbitrary length from one timer, as one of the edges is always bound to the moment of overflow (update). In some newer STM32 there is an option to AND together two channels, but that's not available in 'F0.

However, in the advanced timers such as TIM1, there's a trick possible, where the output's (here, TIM1_CH2) edge is shifted by the dead-time if complementary output (here TIM1_CH2N) are enabled (it's not necessary to actually output the TIM1_CH2N complementary output to a pin, simply don't enable it in GPIO). Note, that the dead-time actually cuts down from the beginnning of CH2 pulse, and you set into CCR2 the moment where trailing edge occurs, not the *length* of the pulse. The not-shifted channel (here, TIM1_CH3) must not have the complementary output enabled. There are limits to the dead time, given by the limited width of TIMx_BDTR.DTR field (and note that it's settings are not "linear"); but 1us should be viable at all reasonable input frequencies.

That would take care of the two pulses and their mutual relationship. Now there's another problem in the task, and that's the overall period. If microsecond resolution is required for TIM1, which is a 16-bit timer, its maximum period is 65536us which is far from the required 1s. To achieve that, TIM1 could be set as slave, in gate mode, with some other timer (e.g. TIM2) as master. TIM1 could then have a shorter period set, e.g. 20us. TIM2 would output a pulse to TRGO exactly 20us long, during which TIM1 would run and produce the pulses on its two output channels; then for the rest of TIM2's period the gate signal would be low (inactive) thus TIM1 would stop (and we'll arrange that it would stop in the moment when both output channels are in low state).

Implemented on L4DISCO (timers are pretty same across STM32 so it should work on 'F0 too): http://www.efton.sk/STM32/tim_delayed_pulse_and_long_period_master_slave.zip (requires http://www.efton.sk/STM32/stm32l476xx.zip ).

For testing, I cut down the "long" period (TIM2's period) to 100us:

Enjoy!

JW

Thank you very much. It really work.