STM32F427 DAC PA4 and PA5 Voltage Spike on Power Down

[Rhodes.Ethan]

Posted on June 30, 2015 at 17:03

I am using the DAC outputs on PA4 and PA5 of the STM32F427 LQFP 100 pin part. On power down, these pins show a voltage spike in the range of 1-3V and 50-100mS in length. It didn't seem to matter how the pins were configured or if they were not configured at all. 

I didn't see this same phenomenon on other pins so I am guessing it is specific to the DAC outputs. I also did not see this when I looked at STM32F429 or a STM32F207 parts. I can't imagine this is expected behavior. Errata did not have any information.Has anyone else seen this? Thank you,Ethan

[Tesla DeLorean]

Posted on June 30, 2015 at 17:12

Not sure why this would be an errata item, the functionality of the part gets into a whole undefined/not-specified space as reality collapses around it.

You're pulling the supplies or SLEEP/STANDBY? If the latter consider reconfiguring the pins as digital outputs driven/pulled low.

[Rhodes.Ethan]

Posted on July 01, 2015 at 01:11

I am pulling the supplies. That is a good point that this is not a defined state. It doesn't seem right that any pin would spike like this as the supplies are dropping to ground, but I suppose in most cases a short voltage spike wouldn't cause an issue. In my case it did, but I have a work around. I thought it may be worth mentioning.

Thank you,Ethan

[waclawek.jan]

Posted on July 01, 2015 at 13:28

Is VDDA within the specified difference from VDD during the powerdown?

JW

[Rhodes.Ethan]

Posted on July 01, 2015 at 17:52

Good question. Yes, VDDA and VDD track closely on power down. They never get close to a 300mV difference.

Ethan

[waclawek.jan]

Posted on July 02, 2015 at 09:32

Things should not be *that* undefined - while VDD/VDDA are nominal even during powerdown, DAC should behave normally until some form of reset reached - powerdown or BOR if the latter is enabled, when

''During and just after reset, the alternate functions are not active and the I/O ports are configured in input floating mode.'' should start to apply, down to the guaranteed operation range (1.7V?), but then where is the 3V spike from? I personally would experiment with - slow powerdown ramps - setting various BOR levels - asserting NRST externally or through watchdog I never used the DAC, though (other than in initial experiments). JW