FAQs
cancel
Turn on suggestions
Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
Showing results for 
Search instead for 
Did you mean: 

STM32F429 FMC + SSD1963 + Clock Speed

matthew2
Associate II

‎2015-05-14 01:18 AM

Posted on May 14, 2015 at 10:18

Hi.

I'm quite new into the STM32 devices, so apologies in advance for the scrappy code!

I've got a STM32F429 Discovery board attached to a SSD1963 display though the FMC (8 bit mode at the moment), however I cant seem to get the display working when the micro is running at full speed.

If I have the PLL-P set to /4 so the HCLK is 84MHz then the display works fine with the settings shown in the code below.

If I set the PLL-P to /2 to run HCLK at 168MHz then I can't find a timing that works correctly.  If I view the signals with a logic probe they look ok but the display doesn't want to respond, so I'm guessing there's something not quite set correctly.  I've tried quite a few different settings for the timing but none seem to work at 168MHz

From the data sheet the FMC runs from the HCLK clock, meaning it has to run at the same speed as the core, so I presume that its just my FMC timing structure that's incorrect.

The initialisation code has been generated using the STM32CubeMX utility.

System Clock Init:

  RCC_OscInitTypeDef RCC_OscInitStruct;

  RCC_ClkInitTypeDef RCC_ClkInitStruct;

  __PWR_CLK_ENABLE();

  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

  RCC_OscInitStruct.HSEState = RCC_HSE_ON;

  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

  RCC_OscInitStruct.PLL.PLLM = 8;

  RCC_OscInitStruct.PLL.PLLN = 336;

  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;

  RCC_OscInitStruct.PLL.PLLQ = 7;

  HAL_RCC_OscConfig(&RCC_OscInitStruct);

  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1

                              |RCC_CLOCKTYPE_PCLK2;

  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;

  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;

  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;

  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); //LATENCY_5 for 168MHz

FMC Init for display interface:

  hsram1.Instance = FMC_NORSRAM_DEVICE;

  //hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;

  /* hsram1.Init */

  hsram1.Init.NSBank = FMC_NORSRAM_BANK1;

  hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;

  hsram1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;

  hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_8;

  hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;

  hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;

  hsram1.Init.WrapMode = FMC_WRAP_MODE_DISABLE;

  hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;

  hsram1.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;

  hsram1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;

  hsram1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;

  hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;

  hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;

  hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;

  /* Timing */

  Timing.AddressSetupTime = 2;

  Timing.AddressHoldTime = 0;

  Timing.DataSetupTime = 2;

  Timing.BusTurnAroundDuration = 0;

  Timing.CLKDivision = 0;

  Timing.DataLatency = 0;

  Timing.AccessMode = FMC_ACCESS_MODE_A;

  /* ExtTiming */

  HAL_SRAM_Init(&hsram1, &Timing, &Timing);    

    FMC_SDRAM_TimingTypeDef SdramTiming;

Any suggestions to get this working with the micro at 168MHz would be very much appreciated thanks!
0 Kudos
3 REPLIES 3
Tesla DeLorean
Guru

‎2015-05-14 07:50 AM

Posted on May 14, 2015 at 16:50

The AHB doesn't have to be the same as the SYSCLK, ie the CPU can run at 168/180 MHz and the AHB at 84/90 MHz

I don't use HAL/Cube, try 

RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2; // AHB Half CPU speed, 84 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // APB1 42 MHz Slow Peripheral
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // APB2 84 MHz Fast Peripheral

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..
0 Kudos
matthew2
Associate II

‎2015-05-14 08:30 AM

Posted on May 14, 2015 at 17:30

Thanks Clive1

This has helped a lot, I can now get the display updating correctly with the sysclk at 168 and the AHB at 84.

Working from an internal frame buffer I can adjust the transfer rate to get about 60ms per frame (320x240).  If I take the timings lower than this the display stops working.  Its not amazing but its a lot better than it was.  Ill play some more with the timing to see if I can get it to update faster.  The SSD1963 should be able to run with much faster timings.

If I use the external SDRAM as a framebuffer, the display doesn't update unless I slow the system clock right down.  Not sure why this is yet because I can read and write to the SDRAM fine if I dont use the display.

I'll keep investigating though.

0 Kudos
davide
Associate II

‎2015-05-14 09:30 AM

Posted on May 14, 2015 at 18:30

Hi matt,

I have nearly the same problem as you here.

I'm working with your exact configuration, take a look at my last discussion on the forum, i have some code that can work also for you! 

Try to fill the frame ( in SDRAM and next to pass it to the SSD thru DMA) with something like 0xF0F0F0 instead of full white 0xFFFFFF. (If I avoid ''solid'' color i get ''legal'' configuration and everything works fine, about 15 fps on a 800x480 in rgb565). Of this I have a description on my discussion.

I don't know why but this SSD thing with SDRAM as frame buffer are a real pain.

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex%5fmx%5fstm32%2fSSD1963%20and%20DMA%20with%20FMC&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&TopicsView=https%3A%2F%...

I hope we'll both find a solution, 

Davide

EDIT: I just see that you also commented mine! Really good post! You have framed the problem, also with mine logic i got the same result:

  • IF an ''illegal'' bit is received from the SSD it will stop listening to the consecutive data. Also, if you repeat the process, mine SSD completely get messed (means that will interpret ''randomly'' data as commands and lose all the initialisation.
  • HINT: From SSD datasheet i see that i cannot be feeded faster than it's PLL/2, i got mine through all possible configuration with mixed results (some where better than other but still doesn't show up the complete frame), now is at 200Mhz.. maybe our problems came from this misalignment of clocks... wild guesses ...
  • Can i ask you what kind of resolution are you driving and what's you're fps goal?
  • My guess is that a certain combination of ''illegal'' data make the SSD to loose sync... but i'm feeling a little bit far from solution... can be that SSD need control command to be pulled up at 5V instead 3.3V?
  • I sure will try the pullup on NWE, i'm running FMC at 84Mhz, but i'm using SDIO and USB for my project so with 168Mhz i can't help, sorry!
  • Here  

    https://youtu.be/Be25GTwIVss

     you can see a short video on what's happening in my board.

I'm thinking that maybe is better to continue our discussion on a single page... mine or yours isn't a problem for me ;)

0 Kudos
Top