Need a solution for external triggered timer NON-retriggerable one shot output

[andrewandrew91]

Posted on March 23, 2018 at 20:34

I am looking for advise on the best way to implement a software enabled one shot external trigger timer that is 

NON-retriggerable

.  So far I have devised a number of solutions but all seem to have a downside either in cpu cylces (software), number or timers required (complex) or external hardware and none of them feel like the elegant solution I was striving for.

Is there a way to do this with timers only?  Not using interrupts or software other than to enable the trigger when needed?

Picture is worth a wall of text right?

https://i.imgur.com/OnrMxCU.png

      Black is 1 MHz external input trigger

      Green is rising edge trigger on 1 MHz input

      Red is desired output pulse

note: moved to questions section as suggested

#timer-external-trigger-non-retriggerable-one-shot-pulse

[henry.dick]

Posted on March 23, 2018 at 21:47

the best would be a timer with a dual compare single shot mode. PIC24 (including dsPIC), PIC32, MSP430, ...

In the STM land, use two single-shot timers chained together, one set to set the output pin, and another set to clear it, ANDing the two outputs with a resistor.

[henry.dick]

Posted on March 23, 2018 at 22:54

the above assumes this functionality you are looking for is part of a larger system.

if it is a dedicated chip, the solution is much simpler.

[waclawek.jan]

Posted on March 24, 2018 at 22:05

I would use the one-pulse mode triggered from an input channel, and a DMA which upon the capture event from the same channel that provided the trigger would rewrite TIMx_SMCR.SMS to disabled. To reenable, software would need to write only that TIMx_SMCR.SMS to trigger mode again.

JW

[andrewandrew91]

Posted on March 24, 2018 at 22:32

Would there be any significant beneficial reason to add DMA for a single half word transfer vs. just using the timer CNT_EN interrupt?   Both methods generate an interrupt and require the MCU to execute code so is this the point where both solutions are basically equal?

This is what I am using right now:

TIM1_ETH triggers on rising edge of external 1 MHz input signal which:

1__starts TIM1_CH1 PWM2 (OPM) OUTPUT LOW->HIGH2__generates an interrupt when the timer is started TIM1_CH1 CNT_EN2a____interrupt service disables TIM1 slave mode with TIM1 SMCR |= TIM_SLAVEMODE_DISABLE

[waclawek.jan]

Posted on March 25, 2018 at 10:40

 Both methods generate an interrupt

Why would any processor intervention through interrupt execution needed, once DMA does everything needed?

JW

[waclawek.jan]

Posted on March 28, 2018 at 02:53

Had a better idea meantime.

It's based on two facts:

- if ARR is shadowed, new value gets reloaded on update, i.e. at the end of a pulse

- if ARR is zero, timer is disabled, no matter what

So the idea is to enable ARR shadowing, and prepare 0 to ARR to be 'activated' at the end of the pulse. Thus, the timer is truly self-disabling.

The 'retriggering' gets a bit more complicated, but IMO it's worth the spared DMA.

http://www.efton.sk/STM32/selfdisable.zip

 

It's for the L4 DISCO and needs some

http://www.efton.sk/STM32/stm32l476xx.zip

. Needs a jumper between PB3 and PB2 to see the LED blink. When joystick moved down, the single pulse occurs. Pressing the joystick middle down 'retriggers'. Does not use any of the extra features of L4 timers, should work straightforwardly on F4 too.

Enjoy.

JW