Posted on May 17, 2011 at 09:54Hello!
We have a problem with programming the new STR912 with 128K+2Mb flash.
When using new ICP algorithm to program 128K flash the process times out and we have a corresponding message. Not-ICP algorithm does not work.
We use KEIL ULINK (not ULINK2 - can this be the reason?), MDK3.22.
We do not have troubles programming STR912FAW44 with its ICP algorithm (128K flash). What's more, we can program STR912FAW47 with algorithm for STR912FAW44. It executes, but we have different problem further.
We configure FMI for STR912FAW44 as follows:
FMI_CR_Val EQU 0x00000018
FMI_BBSR_Val EQU 0x00000000
FMI_BBADR_Val EQU 0x00000000
FMI_NBBSR_Val EQU 0x00000006
FMI_NBBADR_Val EQU 0x00080000
FLASH_CFG_Val EQU 0x00001000
; Setup Flash Memory Interface (FMI)
LDR R0, =FMI_BASE
LDR R1, =FMI_BBSR_Val
STR R1, [R0, #FMI_BBSR_OFS]
LDR R1, =FMI_NBBSR_Val
STR R1, [R0, #FMI_NBBSR_OFS]
LDR R1, =(FMI_BBADR_Val:SHR:2)
STR R1, [R0, #FMI_BBADR_OFS]
LDR R1, =(FMI_NBBADR_Val:SHR:2)
STR R1, [R0, #FMI_NBBADR_OFS]
LDR R2, =FMI_CR_Val
STR R2, [R0, #FMI_CR_OFS]
; Write ''Write flash configuration'' command (60h)
LDR R0, =FMI_BBADR_Val
MOV R1, #0x60
STRH R1, [R0, #0]
; Write ''Write flash configuration confirm'' command (03h)
LDR R2, =(FLASH_CFG_Val:SHL:2)
ADD R0, R0, R2
MOV R1, #0x03
STRH R1, [R0, #0]
Bit CSX (selecting booting from Bank1) is set.
We change the following for STR912FAW47:
FMI_BBSR_Val to 0x02
FMI_NBBSR_Val to 0x08
FMI_NBBADR_Val to 0x200000
On ''Target'' page under project properties we change all 0x80000 into 0x200000 and all 0x8000 into 0x20000.
After executing ''LDR R0, =FMI_BBADR_Val'' command the CPU jumps to Undef_addr handler and we see that debugger in disassembly window identifies all our commands as 0xFFFFFFFF (???).
So,
1. What can be the reason of errors while programming bank1?
2. What is done wrong in FMI configuration?
[ This message was edited by: ekirshin on 31-07-2008 19:05 ]
