Posted on January 15, 2018 at 14:20The SDRAM and LTDC are configured using CubeMX. The SDRAM bank 1 is used as a frame buffer for the LTDC (Layer 1, start address 0xC0000000). I'm using simple verification procedure to check the SDRAM read/write
// 32 bits access
for (uint32_t i = 0; i < 0x2000000; i+=sizeof(uint32_t))
{
*(uint32_t*)(SDRAM_BASE_ADDR+i) = i;
}
for (uint32_t i = 0; i < 0x2000000; i+=sizeof(uint32_t))
{
if (*(uint32_t*)(SDRAM_BASE_ADDR+i) != i)
{
return -1;
}
}
When the LTDC is disabled, everything works fine. When LTDC is on, I have random write errors at different addresses. When looking at the LCD, there are black pixels at the corresponding places. Enabling/disabling L1 cache and/or MPU does not changes anything.
I suppose that LTDC AHB master controller possibly somehow affects the CPU access to the SDRAM. What could this be?
Also when I'm trying to use free part of SDRAM as the data buffer for the emWin, it immediately crashes into HardFault...
