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I’ve been trying to adapt the code from the STM32WB5MM-DK QSPI_ReadWrite_IT example to a Renesas part. However, I have not been able to get it into Quad mode. For this part I need to write 0x02 into register 0x31 as I understand the data sheet.From monitoring the status register I can see that the write enable bit gets set and cleared, but the QE (quad enable) bit doesn’t get set.Also, in reviewing the code for the DK, I don’t see code to set the quad enable bit as per the Infineon S25FL128S data sheet.In searching the support forums, I see references to a routine called QSPI_QuadEnable, but I have not been able to find corresponding code.I’m obviously missing something. Can someone point me in the right direction - either specific to this board or a more generic solution?Thanks

Hello, everyone on the forum.I'm building a system using the STM32H735G-DK, ThreadX, and NetX Duo.I'm writing logs to a microSD card to keep a record of the system's operation.I integrated FTP into the system so that log files can be downloaded via Ethernet.Since the FTP download speed is only about 150 kilobytes per second, it takes a long time to download large log files.Currently, `nx_ftp_server_create` allocates an 8K-byte stack for the FTP server. What are some ways to increase FTP download speeds?I would appreciate any advice. 

Hi,don't  know if it reaches someone who is responsible, but just some thoughts about the datasheets of all the VL53… which i have seen:the NXP documents about I2C which are the defacto standard are stating an address is 7 or 10 bit. So it’s not a question how some microcontroller is handling bit shifting or internal storage of the address, the address of the vl53 is 0x29, not 0x52. If you use Philips/NXP protocol you should follow it’s specification. Please use this in your datasheets.if you talk about SPI it is common to use POCI/PICO or MOSI/MISO and CS/SS/CE…. Why you don’t use the common names for slave select? What should NCS be? Noncommunication Chip Select? Why you transcribe MOSI as "main out secondary in" instead of using common "master out slave in"? If you want to distance yourselves from these terms because of their connection to slavery, then why not use POCI/PICO with "peripheral out/controller in” and vice versa as common.why you describe pins as GPIO if they no one can

Hello, I intend to use two 8-bit DDR3L memory devices with the STM32MP257FAK3. Could you kindly confirm whether this configuration is supported? Looking forward for your response. Regards,Shubham 

I am trying to establish an accuracy figure for our product based on an MPX5500 MEMs pressure sensor.We calibrate at many set pressures across the devices span, so we can reduce non linearity errors.I need to determine the sesnors accuracy with improved non-linearity figues but need to know error corficients for aspects such as temperature, hysteresis, aging etc     There is talk of an orignal “sensor development kit” ASB200 from Motorola (Freescale, then NXP), which had SPICE model.Does anyone know of this kit or have the SPICE models available?Or any other application notes that might help?Thanks. 

I was learning about how the PLLs work on the H7RS boards, and I discovered a small inconsistency in the RCC_PLLCFGR register. On page 440 and 442 of the RM0477, PLL2FRACEN is incorrectly written down as PLL2FRACLEN (including the ‘L’ near the end). I’ve confirmed that this is incorrect by looking at the HAL and seeing it’s consistently defined as PLL2FRACEN in code (without the ‘L’) inside of stm32h7s3xx.h. Searching for the version with the ‘L’ returned no results, so I’ve concluded that this must be a typo in the reference manual. Could you confirm this is a documentation typo?

Hi,I am using an SPC560B40L5 with ChibiOS/AutoDevKit Studio.The hardware design is already finalized, so I cannot change the wake-up circuitry. Because of this limitation, I use the RTC to wake the MCU periodically every 200 ms. After each wake-up, I only check a few GPIOs to determine whether a real wake-up event has occurred. If no event is detected, the MCU immediately enters STOP mode again. No peripherals are reinitialized unless a valid wake-up event is detected.The sleep/wake-up sequence works correctly during normal operation. However, I am facing a strange issue after reprogramming the MCU.After downloading new firmware (without removing power), the MCU freezes in:while (ME.IS.R == 0U){}inside:SPCSetRunMode(SPC5_RUNMODE_STOP);The board must support in-field reprogramming through the diagnostic interface (without a power cycle), but after programming the MCU usually remains stuck until the power is removed and applied again.Interestingly, if I disable the periodic RTC wake-up a

I am trying to establish communication between an STM32F446ZCH6 and a LAN9253 using the Quad SPI (QSPI) interface on our custom hardware.As an initial validation, I am attempting to read the following LAN9253 registers: BYTE_TEST register (0x64) ID_REV (Chip ID) register (0x50) However, I am not receive the expected register values. Instead, the values returned are consistently 0x88888888 or 0xFFFFFFFF.To troubleshoot the issue, I captured the SPI/QSPI communication using a logic analyzer. From the waveforms, it appears that: The STM32 (master) is transmitting the read command correctly. The clock (SCK) and chip select (CS) signals appear normal. However, the LAN9253 does not respond with valid data, and the STM32 does not receive any meaningful data from the slave. We also attempted communication using: Single SPI (1-bit mode) Dual SPI (2-bit mode) Quad SPI (4-bit mode) Unfortunately, the behavior is the same in all three modes, with no valid response from the LAN9253.We hav

Hello Sir/Ma’am,I am planning to interface two 8-bit DDR3L memory devices with the STM32MP257FAK3. Kindly confirm whether this configuration is supported by the STM32MP257FAK3.If supported, I would appreciate your guidance on the recommended implementation approach for this configuration.Thank you for your assistance.Regards,Shubham Kawadkar

Hi ST Support Team,              I am Yashwanth Melwanki, Associated with Quest-Global as Technical Architect.               In one of designs [WIP], we are considering NUCLEO-H755ZI-Q and have connected below Peripherals placed on seperate board. connection is through MROPH headers CN11 and CN12.               All these peripherals will be active and set to run at max speed to the interfaces they are conencted to STM [I2C / SPI / USB / eMMS etc]              I wish to know, What is capacibility of STM32 to run and interact with these peripharals engaged at max speed?                             1. x1 USB FS to USB hub controller              2. x1 I2c to 2 GPIO expanders (24 bit each - one as GPO and Anlother as GPI)              3. x1 I2C to 1 GPIO expander, dedicated as 24Bit GPI              4. x1 Ethernet              5. x2 SPI: One for DAC (16bit, 16 Channel) interface and Another for ADC (16bit, 16 Channel) interface              6. x1 QSPI              7. x2 I2S; One as Inout a

I am using the ST67W611 Wi-Fi module with the ST67 W6X SDK to implement an HTTP web server.While profiling the performance, I observed that every call to W6X_Net_Send() takes approximately 391 ms (or more) regardless of the amount of data being transmitted. Test SetupModule: ST67W611 Interface: SPI Transport: TCP Firmware: 1.1.1 SDK Version : 2.0.89 MCU: STM32F4  QuestionsIs a fixed delay of approximately 391 ms per W6X_Net_Send() call expected? Is W6X_Net_Send() internally waiting for a TCP ACK or another event before returning? Is there any configurable transmit timeout or buffering mechanism that affects this behavior? Is there a recommended maximum chunk size for W6X_Net_Send() to improve throughput? Are there any SDK or firmware settings that can reduce this latency?Any guidance would be greatly appreciated.Thank you.

 Hi， the rear background exceeds 2 meters, and there are no obstacles in front of the sensor. The measurement data is unstable, and the reading sometimes reaches 0 and sometimes reaches 115.      

Hi all,disclaimer: I used AI to translate my question to english:I'm designing the power supply for a solar-charged, battery-powered outdoor device (wildlife camera controller) built around an STM32L476VG. I'd appreciate a sanity check of the architecture and the regulator choices.System:Input: 2S Li-Ion (NP-F pack), 6.0–8.4 V, reverse protection via P-FET MCU in STOP2 most of the time (target sleep budget: < 10 µA for the whole board) Always-on: MCU, RTC (AB1805), I2C EEPROM, a µA-class wake-up receiver Switched loads (active phases only, seconds to minutes): LoRa module (TX approx 120 mA), SD card (write bursts approx 100 mA), OLED, GPS Separate 5 V rail (TPS62147, EN-gated) for a Raspberry Pi that wakes for uploadsCurrent design: one 3.3 V rail from an MCP1703A (2 µA IQ, 250 mA), all loads behind individual load switches (TPS22919 etc.).Concern: worst-case concurrency (LoRa TX + SD write + MCU + OLED) sums to approx 250 mA -right at the LDO's limit, and (8.4 − 3.3 V) × 0.25 A app

Hi,I’m using TESEO-VIC3D for PPS generation for time synchronization and OCXO frequency correction. I wanted to use PSTMPPSDATA NMEA messages in order to read quantization_error parameter and apply it in my program to eliminate the quantization error of PPS signal. Mostly it works well, but I ran into couple of issues:There is a ref_sec parameter in the PSTMPPSDATA message that should refer to a specific second for which the message corresponds. For some seconds, this message is missing, e.g.:2026-07-11 17:43:09.564 $PSTMPPSDATA,1,1,1,0,0,0,0.500000,0,633,420,420,633,0,0,0,0,0,11,3,5,18,4,0,0,6.622e-09,65473709.68,48000018.67,4*242026-07-11 17:43:09.567 $PSTMTRAIMSTATUS,1,0,15,7,5,2,11*542026-07-11 17:43:09.573 $PSTMTRAIMUSED,1,5,7,21,11,16,9*7C2026-07-11 17:43:09.576 $PSTMTRAIMRES,1,5,-3,-9,6,-3,10*162026-07-11 17:43:09.580 $PSTMTRAIMREMOVED,1,2,30,4*2F2026-07-11 17:43:10.616 $PSTMTRAIMSTATUS,1,0,15,8,5,2,12*582026-07-11 17:43:10.620 $PSTMTRAIMUSED,1,5,7,21,11,16,9*7C2026-07-11 17:43:

The errata sheet for the STM32U585 (ES0499) is no longer listed in the documentation section on the product page, and the old download link now returns a 404 error. For reference, the following post includes a download link for ES0499 that no longer works. https://www.st.com/resource/en/errata_sheet/es0499-stm32u575xx-and-stm32u585xx-device-errata-stmicroelectronics.pdf How can this document be retrieved?  Thanks,Owen

Are there any single MCU + LoRa 2.4 GHz ICs in the world?

I used STM32F103 in a mix configuration of bare-metal&HAL supplied by STM32CubeMX. I'm not sure ST can provide the documentation that can be referenced to generate the SBOM for cybersecurity purpose. Is there any recommended tool to scan the firmware project folder. If ST is yet to provide a way to auto-generate SBOM for cybersecurity requirement, possible to use manually curated SPDX-based JSON format for machine processing. If anyone had gone through similar process for regulatory review, can you please share the experience? Any inputs/advise would be greatly appreciated. Thank you.

In the stm32 cubeMX Board selector menu I cant find board MKI-109D.How can I develop the board firmware? 

Hello, we are testing using an STM32H7R7L8H6 paired with an IS42S32800L-6BL. There are no data failures at 100MHz, but data failures occur after prolonged execution at 150MHz. What is the maximum FMC execution speed of the STM32H7R7L8H6? This test was conducted with the MCU DVDD pin unconnected. Is this related to the DVDD pin connection?

Hello,I am debugging USB function on STM NUCLEO-H723ZG demo board. I set the USB_DEVICE Mode as CDC(Virtual Port) mode. USB_OTG_HS can as below.Now I can get the virtual port number on the computer. But the VBUS over current LED (LD7) is always on. It indicates the VBUS over current. But I have configured the EN pin of STMPS2141STR as high (Set PD10/USB_FS_PWR_EN) to disable this fault. Can anyone please help to check what’s the problem? Thanks, 

Setup  - MCU: STM32U595VITxQ (Cortex-M33)  - ADC: ADC4, 57Mhz，12-bit, 7 channels, 6400 Hz sample rate, triggered by TIM1  - Data path: GPDMA1 in linked-list circular mode, double-buffered with half/complete callbacks (128 samples per half-buffer). DMA writes directly into a static INT16U s_adc4_result[256][7] buffer in normal SRAM.  - Signal chain: external current/voltage sensors → signal conditioning board (op-amps, anti-alias filter, DC bias) → ADC4 input pins  - Firmware: FreeRTOS, half-callback copies 128 samples per channel into a ring buffer (PF_TOTAL_WAVE_NUM = 40 slots × 128 samples), pf_task consumes from queue  Symptom  Most of time, everything works fine. But some times something wrong happened，in a log file we captured, channels simultaneously read byte-identical constant values.Questions:  1. Has anyone seen an STM32U5 ADC report "healthy" (no OVR, no error, ADSTART set) while consistently delivering a constant code per channel? Are there silicon errata I should check?  2

I spent a lot of time designing a prototype using the STM32H573MIY3Q, but now it’s out of stock (DigiKey/Mouser/JLC) and 78 week lead time (available Jan 1, 2028). I’m kicking myself for not asking earlier about STM’s commitment to this part.How do we get samples now? I guess I can go to the scalpers...But then is it even smart to design this into a product? What is STM’s planned production ramp?Initially I’ll sell a few hundred units but if it goes well I might need 10K+ per year.Am I delusional in hoping for the possibility?I apologize for my tone of frustration, but SEVENTY EIGHT WEEK lead time is hard to believe, and upsetting. Is this not a flagship microcontroller (STM32H5) and flagship package (WLCSP-80)?

Hi everyone,I'm working with the STM32F446RE and exploring the 6-step BLDC motor control example provided by the STM32 Motor Control SDK. In the CubeMX configuration of the firmware:3 GPIOs are configured as analog inputs:M1_BEMF_U → PC3 → ADC1_IN13M1_BEMF_V → PA7 → ADC1_IN7M1_BEMF_W → PB0 → ADC1_IN8However, in the ADC Injected Conversion Mode, only Channel 13 (PC3) is selected and used (1 injected conversion configured).See image below for reference:My question is:Why are all 3 BEMF pins configured in CubeMX if only Channel 13 is used in the ADC injected group?I expected that all 3 channels would be used in the injected sequence to sample U, V, and W BEMF voltages.Do they dynamically change the injected channel in code depending on the commutation step? Or is there another reason for this configuration?Thanks in advance for any clarification!

Hello Team,I have used STM6824SWY6F Part in one of my Design and I’m performing a de-rating analysis, so could you please share the below details,1. Junction Temperature2. Junction-to Ambient Thermal resistance3. Junction-to-case Thermal resistance4. Maximum power dissipationThanks,Deva

Hi everyone,I'm designing a custom development board based on the STM32H750XBH6 and originally planned to use the ISSI IS42S32400F-6BL (128 Mbit, 4M × 32, SDR SDRAM, 166 MHz, 90-ball BGA).However, this part appears to be obsolete/end-of-life, and availability is becoming an issue.I'm looking for recommendations for a newer SDRAM that is:Fully compatible (or requires minimal hardware/software changes) 128 Mbit or larger 32-bit data bus 3.3 V SDR SDRAM 166 MHz (or higher) 90-ball BGA (preferred) Currently in production and readily available from major distributorsHas anyone recently designed an STM32H750/H743 board and selected a newer SDRAM instead of the IS42S32400F-6BL?I'd appreciate recommendations for specific part numbers that are currently in production and known to work well with the STM32 FMC interface.Thanks in advance!