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The WL series is great, but unfortunately there aren't any chips with more than 256KiB flash and 64KiB RAM. This appears to be a serious limitation for a SoC with LoRa connectivity.The value proposition of this series is that you pay for one package that provides both connectivity and compute, which is cheaper than paying for 2 separate ICs. I'm personally working on a project where this small memory is beginning to be an issue, and I might end up having to separate those ICs.It kind of seems strange to me that the G0 "entry-level" series comes with much more memory - up to 1MiB / 144KiB.Are there any plans to bring out WL series chips with more memory?Thanks

I am using CUBEMX Version      6.17.0STMCUBE IDE                            2.1.0FW Package name & version     STM32Cube FW_H7 V1.13.0Enabled LWIP ETH With FREERTOS CMSIS2same settings did with cmsis version 1 it's working but with cmsis version2 NOT WorkingI configured on internal Timer TIM1 as soon as I connect Eth Cable program counter not reaching threads & Timer callback / TIM6(systick update).I checked in fault handlers it is not reaching here ETH State in eth handler is (READY STATE --> START STATE)Error code in eth handler is zero.Here I have attached my .ioc fileI have updated flash ld file as per repository code LWIP Debug Messages :

Hi, As per UM3610 « section 7.7 », a "Bootloader limitation" has been found in NUCLEO-WBA25CE1. Please refer to "Workaround" section if you are facing this limitation.

 I am using CUBEMX Version   6.10 STMCUBE IDE                        1.16.0FW version                               F7V1.17.0Enabled LWIP ETH With FREERTOS CMSIS2same settings did with cmsis version 1 it's working but with cmsis version2 NOT WorkingI configured on internal Timer TIM1 as soon as I connect Eth Cable program counter not reaching threads & Timer callback / TIM6(systick update).I checked in fault handlers it is not reaching here ETH State in eth handler is (READY STATE --> START STATE)Error code in eth handler is zero.Here I have attached my .ioc fileI have updated flash ld file as per repository code LWIP Debug Messages : netif: netmask of interface set to 255.255.255.0 netif: GW address of interface set to 192.168.10.10 netif_set_ipaddr: netif address being changed netif: added interface

Split from Transmit line stuck high on STM32F415 with MAX3232 - this is a new questionWhat ST board would you recommend? This is not really my realm. Thanks!

Trying to program the option bytes I get the error message shown below. Can someone tell me what is wrong? I have tried with and without the displ and I have also tried with only one option byte at the time.C:\Temp\BMSM-18>"C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin\STM32_Programmer_CLI.exe" -c port=SWD -ob TZEN=B4 SECWM1_STRT=0x0 SECWM1_END=0x0 SECWM2_STRT=0x1f SECWM2_END=0x0 displ-------------------------------------------------------------------STM32CubeProgrammer v2.22.0-------------------------------------------------------------------ST-LINK SN : 003F00383234511537333934ST-LINK FW : V3J15M7Board : STLINK-V3MINIEVoltage : 3.29VSWD freq : 8000 KHzConnect mode: NormalReset mode : Software resetDevice ID : 0x478Revision ID : --Device name : STM32H533/523NVM size : 512 KBytesDevice type : MCUDevice CPU : Cortex-M33BL Version : 0xE2SFSP Version: v1.2.0Debug in Low Power mode enabledError: Wrong command -ob tzen=b4 secwm1_strt=0x0 secwm1_end=0x0 secwm2_strt

This error pops up everytime I try creating a new STM32 project when downloading the selected files during the first stages of creating a project. My internet connection is fine and this wasn't an issue some weeks back with the last project I created. Any assistance on this issue from anyone will be very helpful because I'm a quite a newbie to CubeIDE. Thanks.

I was trying to implement emulated EEPROM and I think I set the EEPROM page area right into the critical option bytes area. Notably, this didn't happen until I added the actual eeprom_emul.c and flash_interface.c files into the cmake configuration, compiled and flashed the program once. This obviously makes a call to "HAL_FLASH_UNLOCK()" so I think it's pretty messed up. Either way, after this, I could not flash the chip beyond 0x80000050, additionally, it would instantly lock up on boot. I believe my Option Bytes were also grenaded.  PCROP_RDP turned itself on, ESE turned itself on and the rest I am unsure of changes. Either way, I managed to turn off RCROP_RDP by setting RDP to 1 and then to 0. After this, flashing the chip, fills every line with the same repeating nonsense bytes. So I think write protection is disabled, but it's still uploading nonsesen. Notably, trying to hit "full chip erase" does not work, and just hangs. Now ESE remains checked. When trying to uncheck

Hi!I'm building a device using a STM32U31xx, connected to a Network Chip via I²C (PB6/7) and 2 GPIOs for Reset and BOOT0 Pin. The intention is to have new firmware downloaded onto the network chip, and flash new firmware to the STM32U031 via the system bootloader.I power up the system to invoke a power up reset on the ST device, I immediately flash firmware and ask the chip after another reset cycle for the new firmware version to confirm the new firmware was flashed.The behavior I observe is the following:- if the STs Option Byte nBOOTSEL is 0, the process works just fine, very reliably.- if nBOOTSEL is 1, the process fails even if I mass erased the STs flash memory entirelyThis is contrary to my understanding of AN2606 Table 2, pattern 11, that states that the empty check should start the system bootloader no matter the state of nBOOTSEL bit or BOOT0pin.I intended to have the ST chip flashed on production without previous intervention into the STs option bytes (nBOOTSEL is 1 on deliv

Hello,I am writing this because I am unable to enable the SAI on this development board. The strange thing is that I actually managed to enable it before and it was working correctly. However, while implementing another feature, I switched branches and worked on a different GitHub branch for some time. When I came back, I noticed that the SAI was no longer starting.At first, I thought I had made a mistake in a commit, so I created a completely new project where the only goal was to start the SAI. Even though I believe all the steps are configured correctly, the MCK clock never starts, and the MCKEN register bit never becomes enabled. I am attaching screenshots of the SAI registers below. As shown in the screenshot, the SAI is enabled, but I cannot see any clock output on the oscilloscope. As I mentioned before, what confuses me the most is that two weeks ago, using the exact same development board, I was able to make it work correctly.I tried adding the following line inside the M

Hi all,I'm looking for recommendations on eMMC chips that are known to work reliably with the STM32H743 via SDMMC1 in 8-bit mode.I've gone through a number of threads here and put together what I've found so far:- Micron 4GB (MTFC4GACAJCN) — comes up often, though some posts mention HAL misreading certain CSD fields (appears cosmetic rather than functional)- Kingston 4GB — confirmed working with SDMMC1 + FatFS + FreeRTOS, corruption reports seem tied to FatFS rather than the chip itself- Samsung KLM series — functional but VCCQ voltage negotiation adds complexity- Kioxia THGBMDG5D1LBAIL — 153-ball WFBGA, eMMC 5.0, fewer reports but looks promisingHappy to keep things simple — 3.3V on both VCC and VCCQ, no need for HS200/HS400.Would love to hear from anyone who has had long-term success with a particular chip, or any that are worth avoiding. Any layout tips for the 153-ball WFBGA package are also welcome.

I'm using an STM32H7S78-DK with TouchGFX and FreeRTOS. I would like to limit the framerate of the target to 30fps but withouth reducing the LTDC frequency.Basically having the VSYNC fired at 30fpsI've already set the  ((touchgfx::HALSDL2*)&hal)->setVsyncInterval(33.333);In the simulatorIs there a way to force it on the target?

Is there any utility in the holes and silkscreen circles around the TFBGA225 on the NUCLEO-H7S3L8?  It appears to be the same pattern on the Discovery board, suggesting it might be for BGA placement or maybe a heatsink. Edited to put the image in-line for better visibility

Hello Team,We are using the internal SMPS configuration for the core power supply. However, the power-up sequence does not specify the timing requirements for the different stages.Could you please provide the timing details for the following? What should be the time duration for the PWR_ON signal to transition from low to high while VDD and VDDA18AON are rising (Step 1)?After PWR_ON goes high, what is the required time duration for VDDA18PMU / VDDSMPS to rise (Step 2)?What is the exact meaning and function of the SDEN signal?Are there any additional considerations or recommended guidelines to be followed during the power-up and power-down sequence? Thanks 

Hi, hope you doing good,In our design, we are using the ST60A3H1C1CCEPY3 controller. please clarify if there are any layout restriction or keep-out zones around the controller where other peripherals should not be placed.Thanks,

Hello, I am using an **STM32 NUCLEO-N657X0-Q** board with the **B-CAMS-IMX camera module**. Originally, the board was working correctly. In **DEV BOOT mode**, I loaded and ran my AI model, using the B-CAMS-IMX camera sold by ST. The board connected normally to my laptop, and I was able to confirm that the AI application was running correctly by viewing the camera output and the AI object detection result on my laptop. I also changed the BOOT pins and confirmed that the same AI application worked correctly in **Flash Boot mode** as well. After that, I wanted to test whether the board could run from an external power supply instead of being powered through ST-LINK. So I changed **CN9 from 1-2, STLK power, to 5-6, VIN power**, following the description in the official NUCLEO-N657X0-Q documentation. Then I applied **7V from a DC power supply to the VIN and GND pins** of the NUCLEO-N657X0-Q board. I carefully checked the polarity and connected VIN and GND correctly. When I supplied 7V throu

Hi, can someone please check what is wrong here: CubeMX/CubeIDE generates an STM32WB55 linker/memory map that places .MB_MEM2 in an SRAM2 region that bus-faults after the installed wireless stack reserves/protects SRAM2. A manually adjusted linker script placing MB_MEM1/.MB_MEM2 at 0x20038000 works.  Observed: Generated/bad .MB_MEM2: 0x200301E4..0x20030A67Edited/Working .MB_MEM2: 0x200381BC..0x20038A3F The CubeMX-generated .ld file gives this fault:HardFault before main()CFSR = 0x00000400 = IMPRECISERRStacked PC = 0x080048CE, inside LoopCopyDataInitR0/R1/R2 match .MB_MEM2 copy bounds Attached .map .ld  .ioc> STM32_Programmer_CLI.exe -c port=SWD freq=1000 mode=HOTPLUG -fusgetstate-------------------------------------------------------------------STM32CubeProgrammer v2.20.0-------------------------------------------------------------------ST-LINK SN : XST-LINK FW : V2J47S7Board : --Voltage : 3.30VSWD freq

Hello STM Team,I have been trying to get the GC2145 to work on the DK but no matter what i do i only get /dev/video0 but never /dev/media0I use Buildroot with the Linux kernel on ST's Github. I have followed this guide here: https://wiki.st.com/stm32mpu/wiki/STM32MP13_V4L2_camera_overview and i have all the Kernel modules needed activated.I know the camera is plugged in properly because the demo from ST works but there's no code or config that goes along that demo for me to find the issue, at least i could not find it.I will attach a little bit of debug info at the bottom if its any helpful:# dmesg | grep -i gc2145 [ 0.058299] /soc/bus@5c007000/i2c@4c006000/stmipi@14: Fixed dependency cycle(s) with /soc/bus@5c007000/i2c@4c006000/gc2145@3c [ 0.058443] /soc/bus@5c007000/i2c@4c006000/gc2145@3c: Fixed dependency cycle(s) with /soc/bus@5c007000/i2c@4c006000/stmipi@14 [ 0.069826] /soc/bus@5c007000/i2c@4c006000/stmipi@14: Fixed dependency cycle(s) with /soc/bus@5c007000/i2c@4c006000/gc2145@3c

Hello Team, Hope you are well! Could you confirm if the following top marking on ST4SI1M0008SCIFW is correct? 8942310525 000000923 FN527 Many thanks! Robert

Hello,I used the SPV1050 chip to connect the circuit to the STEVAL-ISV019V1 evaluation board, and measured VSTORE to be 3.9V, which did not reach VEOC and naturally did not have LDO2 output. I use the STORE pin to power my sensor node load. May I ask which part of the energy I am using at this time is from the battery?Besides, how can I make VSTORE rise to VEOC? Why hasn't my VSTORE changed under prolonged exposure to light.Can the final LDO2 output supply power to the load, or can it only serve as a reference voltage for certain devices.Thank you for your reply.

Split from  ST87M01 : MAX length of the data returned by AT#IPREAD - which is solved.This is, indeed, a new question.Hello Didier,I have an additional question on this topic (I don't know if I should create a new post, but this question is very much linked to the previous one...) :- From the ST87MXX AT Command User Manual §9.8 AT#IPSENDUDP, the max IP frame size is 1400 bytes- But from ST87MXX TCP/UDP-IP Application Note §3.2 IP default parameters command, the max IP frame size is 1600 bytes,Is there a mistake in one of these documents, or is there something that I didn't understand ?Best regardsThierry

Hi, As per title I am unable to enter the System Memory bootloader when using the STM32C071FBP6N. Any assistance would be greatly appreciated. Following the notes in AN2606, i have configured pattern 11 (line 2) using the CubeProgrammer but when completing the reset with the Boot0 pin high it does not enter the bootloader mode and can tell this because my user application runs immediately after the reset occurs. I have been able to jump to the bootloader through my own firmware where I initialize the HAL and GPIOs and then check the status of the boot0 or other pins then manually change the PC and SP but wish to avoid this method as this should not be necessary. ------- I have followed the steps below: 1. Using a ST-Link I have successfully changed the option bits nBOOT_SEL=0; nBOOT1=1; nBOOT1=1; BOOT_LOCK=0 using the CubeProgrammer and have also flashed a basic UART output program which outputs to USART2 the whether the PA14/BOOT0/PA15 is high or low. 2. disconnect the ST-Li

Post edited by a ST moderator. Please use English in this community. Please read How to write your question to maximize your chances to find a solution   手册上写着在高分辨率模式下功耗 90 µA，在低功耗模式下功耗低于 1 µA。可是我用示波器串联电阻抓出来的功耗接近1MA，并且未使用MCU配置传感器时功耗就已经接近这个值了。传感器通过开发板的3.3V接口进行供电。电路图如下所示，哪里存在问题呢？ Translation: The manual states that the power consumption is 90 µA in high-resolution mode and less than 1 µA in low-power mode. However, the power consumption I measured with an oscilloscope using a series resistor is close to 1 mA, and this value is already close to the power consumption even without configuring the sensor using the MCU. The sensor is powered through the development board's 3.3V interface. The circuit diagram is shown below. Where is the problem?

I am working on SDRAM execution using FMC on STM32H563ZI (NUCLEO-H563ZI board) with external SDRAM connected through FMC interface. Our target is: Execute application sections from SDRAM Place heap and stack in SDRAM Enable automatic scatter-loading/copy from internal flash to SDRAM during startup We are facing an issue where: SDRAM initialization appears successful Manual SDRAM read/write access works in application runtime But automatic copy/scatter-loading from Flash to SDRAM during startup is failing Application execution from SDRAM is unstable and leads to HardFault/reset handler Below are the detailed steps and observations. CURRENT STARTUP FLOW Reset_Handler→ SystemInit()→ PLL/System clock configuration→ FMC GPIO configuration→ FMC SDRAM initialization→ SDRAM command sequence→ __main()→ scatter loading→ main() We intentionally moved FMC/SDRAM initialization into SystemInit() so that SDRAM becomes available before scatter loading. CLOCK CONFIGURATION We configured P

Is it possible to use the awesome MDF and/or ADF on STM32U5 with input data from RAM? I have not found any configuration for BSMX for this. One use case is an high performance external delta-sigma-demodulator (ADC) on SPI with proprietary data format (24 Bit per channel, MSB first, CRC etc.) for providing the sound data. Another use case is an LSM6DSV16XTR, also connected via SPI.