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i’m trying to use stm32h735 chip in my custom board , when it comes to flashing or starting new debug session it gives error like   when i’m trying to access it through stm32programmer it gives it work and connect after many times of trying to turn off power, or remove the st link cable and put it again, when it connected, I erase the full chip to access it, then try to flash it in the ide, it works for 3 times, then repeat the error again, and I tried in cube programmer to change the mode to under reset mode and press reset button and press connected, it failed, I need to know permanent solution not every time it gives me this 

Dear ST Team,  We have recently received parts of STM32G474CET6 & STM32F103RBT6 which there are no COO information on Label. Is this normal observation?  Could you please help advise if this is due to label format restriction of tariff issue or other reasons? All the COD and COO info the parts are visible on chip itself. Appreciate your explanation and advise.   

Hello STMicroelectronics Community,We are evaluating the following STM32 microcontrollers for long-term use in our drone flight controller development: STM32G431 STM32G431KBU6 STM32G474VET6 STM32H743VIT6 STM32H723VGT6 We would like to understand the long-term market availability and product lifecycle commitment for these MCUs.Could you please clarify the following points? Product Longevity: For how many years will these MCUs remain available for purchase and production? Lifecycle Status: Are these models active, recommended for new designs, or approaching end-of-life (EOL)? Long-Term Supply: Does STMicroelectronics provide a guaranteed supply period or product longevity commitment for these specific MCUs? EOL Notification: If any model is planned for discontinuation, how much advance notice will be provided? Replacement & Migration: If a model becomes obsolete, will a pin-compatible or functionally compatible replacement be available? Our concern is to avoid selecti

I need the CPU to copy camera frames for tasks like screenshot-based recognition and uploading. However, in the data path (sensor → CSI → DCMIPP → DMA → DDR), the DMA mapping layer marks the memory as uncached, resulting in very slow speeds; the CPU read bandwidth is only ~143 MB/s—just one-eleventh of the speed of standard cached memory (1619 MB/s).Copying a 1280x960 image from DMA takes around 25ms, and the process becomes even slower at higher resolutions, leading to a poor user experience.Is there a way to make the DMA copy speed match that of standard cached memory (1619 MB/s)? 

Hi, Good DayI am Mike, I work for Lenovo Japan, I am currently doing a POC for ML enabled embedded application using STM32N6570-DK. I just got stuck after debugging incremental update to my firmware (add ThreadX). Background / PretextWith the help of https://community.st.com/stm32cubeide-mcus-28/stm32n6570-dk-debug-keeps-failing-error-32-load-failed-not-sure-if-i-should-debug-fsbl-or-appli-168613?tid=168613&fid=28, and STMicro Template_Isolation_XIP project, I was able to setup a project that runs debug from FBLS to AppS to AppNS. I plan to build my target firmware bit by bit, and so I was able to add UART1 for debug log and it was working at that point.My next step was to add ThreadX, so I configured .ioc to add ThreadX and TIM6 as source clock to SYS_NS, then I forgot to turn on the RTOS awareness to ThreadX->CoreM55 and I begun to fail connecting when hitting debug.I kept a copy of basic Template_Isolation_XIP that was perfectly working, and event switching to that project, t

Hi everyone,I'm using UART Receive-to-IDLE with circular linked-list GPDMA on an STM32H7RS and ran into a problem where reception stopped with HAL_DMA_ERROR_DTE.The DMA node and RX buffer are both in DMA-accessible, non-cacheable RAM and aligned to 32 bytes.The DMA handle and queue structure are in normal BSS. Everything is global/static and zero-initialized.I checked the queue/node connection and the source address in LinkRegisters[3], which correctly pointed to UART RDR. The node address reconstructed from CLBAR and CLLR was also correct when checked.However, these were the actual DMA register values in the working and failing cases: Working FailingCBR1 0x00000080 0x0000049BCSAR 0x40007824 0x00000005CDAR 0x24001960 0x200065A0After the DMA error, UART error handling stopped reception and disabled the IDLE interrupt, so I stopped getting HAL_UARTEx_RxEventCallback() calls.What fixed it was adding __DSB() inside HAL_DMAEx_List_Start_IT(), after the CLB

Hello,I am using:- NUCLEO-F401RE- X-NUCLEO-53L4A1- VL53L4CD_GUI (Rev 1.0.17549)The VL53L4CD sensor is working correctly with the X-CUBE-TOF1 example(53L4A1_SimpleRanging). I can read distance measurements through theST-Link Virtual COM Port.However, VL53L4CD_GUI cannot detect the sensor.When the GUI starts, it shows:"Failed To Connect to Nucleo Board: Com Port Not Detected"After pressing "Flash FW", it changes to:"COM9 Connected: Sensor Not Detected.Please ensure sensor connected then Press Black Reset Button on the Nucleo."Additional information:- ST-LINK is detected correctly.- STLink Virtual COM Port (COM9) is available.- STM32CubeProgrammer can connect successfully.- The VL53L4CD sensor is confirmed to be working with the  53L4A1_SimpleRanging example.- The GUI remains in OFFLINE MODE and API Version shows TBC.Has anyone successfully used VL53L4CD_GUI withNUCLEO-F401RE + X-NUCLEO-53L4A1?Is there a specific firmware required for the GUI?Thank you.

Hi ST Community & Support Team,I am working with the NUCLEO-H755ZI-Q (Board MB1363) and I noticed a potential typo in the User Manual UM2408 (Rev 6). 31/57In Section 7.12 - Ethernet, Note 3 states:"On MB1363 Rev.C: Ethernet PHY LAN8742A must be set in the Power-down mode [...] SB13 can also be removed to get the same effect."However, when checking the schematic (mb1363-h755ziq-d01_schematic.pdf), SB13 is actually located in the ST-LINK Virtual COM Port level translator circuit (U1: SN74LVC2T45DCUT) between STLK_VCP_RX and T_VCP_TX, and is already marked as DNF (Do Not Fit).It seems SB13 in Note 3 is a documentation typo pointing to the wrong solder bridge.Based on the schematic, there is no dedicated hardware jumper or solder bridge (SB) to physically disconnect the power or clock lines of the LAN8742A PHY.Furthermore, upon a detailed review of the schematic, there is no dedicated hardware jumper or solder bridge (SB) to physically disconnect the power or clock lines of the LAN8742

STM32CubeMX 6.18.1 + STM32Cube FW_G4 1.28.3Target: STSPIN32G4 / TIM1Asymmetrical Dead Time enabledCubeMX GUI:Dead Time = 50 Falling Dead Time = 50 Asymmetrical Dead Time = EnableGenerated LL code:C  TIM_BDTRInitStruct.DeadTime = 50;No write to TIM1->DTR2 is generated.Runtime observation:DTAE = 1 DTGF = 0Therefore CubeMX appears to generate DTAE but not DTGF.

Hi, Folks.I’m using a board with NUN code ending in $CR1, C260400252, MB...Q-C02 if that includes useful rev info.I started powering this ST Nucleo board with +12 from a bench supply, limited at 600 mA, into CN3 pin 24 with ground on pin 20 (19,20,22 all ground) and that was being regulated down to +5 by U25 just fine.  So I let the board see the +5 by inserting CN9:5-6 jumper.With nothing plugged in but power, LD1 was on (green), LD9 red on and green flashing, LD4 red on faintly, LD5 flashing red.  All this as expected except the state of LD9 which appeared to be due to 3V3_STLK existing (regulated from 5V) but no USB connection.  I checked and recorded all the voltages on CN2; everything looked reasonable except pins 9 and 10 pertaining to the internal SMPS which is free floating, because by default VDD1V8 is not being generated (low nonzero voltage at TP14).I was about to plug the cable I’d made into CN1 when I noticed LD5 had stopped flashing and the current being drawn from my 12V

In release configuration, the flash usage is 65%,but in debug configuration, it is 98.1%. What’s more ,when i download my app to stm32f103c8t6, it will be debug configuration.

I'm looking into the best way to control the brightness of an LED load using PWM from an STM32 and would appreciate some advice on the practical side of the implementation.My understanding is that the average brightness can be controlled by changing the PWM duty cycle while keeping the LED supply voltage constant. For example, increasing the duty cycle should increase the average current and therefore the perceived brightness.What I'm less certain about is choosing an appropriate PWM frequency. A very low frequency could potentially result in visible flicker, while a much higher frequency increases the number of switching events.For a longer LED load, I'm also wondering whether it is better to keep the STM32 PWM output isolated from the actual LED current path using a dedicated MOSFET or LED driver.If anyone has implemented PWM-controlled LED lighting with an STM32, what PWM frequency and timer configuration have you found to be a good starting point?I'm particularly interested in the

Hi there, I am trying to to set up IEEE 1588 PTP time synchronisation with the Netx Duo IP-Stack. I want to port the STM32N6 example (https://github.com/STMicroelectronics/STM32CubeN6/tree/main/Projects/NUCLEO-N657X0-Q/Applications/NetXDuo/Nx_PTP_Client) to my STM32H563 / Nucleo-H563ZI.To my understanding, the H5 Series support PTP and should be able to run the example. The programm runs and prints out the MAC-clock, but the time does not increment and stays always on the same value of 0 seconds and 0 nanoseconds.I also tried to examine the PPS Signal on PG8 with an oscilloscope but as there is no running MAC clock, I get no PPS Signal.To fix this issue I tried different clock increments, thread-priorities. My guess is that the PTP clock in the MAC and the PPS output have to be activated seperately, but I wonder how? Thanks

I’m using an Infineon SEMPER NOR flash (JEDEC manufacturer ID 0x34; S28HS512T) with the STM32H7S78-DK XSPI2 interface. The bootloader uses STM32 External Memory Manager’s SFDP NOR driver, configured as EXTMEM_LINK_CONFIG_8LINES. The device has a hybrid sector map, and I’m updating mapped sectors from firmware stored on an SD card.The updater compares each logical sector, erases sectors marked for update, then writes the corresponding firmware data. Block-protection setup reports success: CLPEF (0x82), writes to CFR3V and STR1V (0x71), and a DYB unprotect write (0xE1) all return HAL_OK.For sector index 33, at address 0x00040000, size 262144 bytes, erase returns EXTMEM_OK (the measured duration was 0 ms). The subsequent write fails before any page-program command is sent: the driver’s initial WIP poll times out after 5 seconds.FW erase begin idx=33 logical=0x00040000 cmd=0x00040000 size=262144FW erase end idx=33 ... status=0 elapsed_ms=0FW write begin idx=33 addr=0x00040000 ... bytes=262

Hi everyone,We are facing an issue with the RTC on our custom hardware based on the STM32N655X0 MCU and would appreciate any suggestions to help us identify the root cause.1. Project OverviewWe have configured the RTC in our application, and maintaining the correct time across power cycles is an important project requirement.Our firmware is stored in external flash. During development, we use J-Link for programming, and we have also implemented firmware flashing through USB using an FSBL with DFU support.Both flashing methods work successfully. However, we have observed unexpected RTC behaviour after flashing and subsequent power cycles.2. Issue DescriptionAfter flashing the firmware, if we remove the main supply (VDD) and power the board back on after a few minutes, the RTC does not account for the elapsed time correctly.For example, if flashing completes at 12:25 PM and we power off the board immediately, then power it back on at 12:30 PM, the RTC does not reflect the five-minute int

Hi, I'm designing the STUSB4500QTR into a board that can run from USB-C, PoE or a DC jack. VDD is on VBUS as usual, and I'd like to run VSYS (pin 22) from our 3.3 V supply instead of grounding it, so the part can't hold the shared I2C bus low when the board is powered from PoE or the jack and USB-C isn't plugged in. DS12499 Rev 8 seems to say two different things:- Section 6.1.1 (p. 23): "there is an interest in using VDD pin only to supply the STUSB4500. First of all, this is mandatory to enable VBUS input voltage monitoring."- Table 22 (p. 29): the VTHUSB (VBUS disconnection threshold) and VTH0V (vSafe0V threshold) rows give the condition "VSYS = 3.0 to 5.5 V". The table header says "Unless otherwise specified: VDD = 5 V, TA = 25 °C", so I can't tell whether those rows were measured with VSYS only, or with VDD and VSYS both present. My questions:1. With VDD on VBUS and VSYS at 3.3 V both present, does the STUSB4500 still monitor VBUS (VBUS_VS_DISCH, detach detection, and discharge at

I am experiencing a critical issue with the hardware video encoder (VENC) on the STM32N6 when processing low-light frames.Setup: Sensor: IMX335 connected to STM32N6 Capture Pipeline: DCMIPP configured in 1080p@15FPS capturing and writing to RAM in RGB565 format. Encoder Input: The same RGB565 buffers are passed to the VENC. Storage: The encoded H.264 stream is saved directly to an SD card. The Problem:When the camera enters a dark environment (very low-light conditions) and I manually reduce the Gain/Exposure to very low values (where the image should be almost completely black), the video recorded on the SD card starts to progressively brighten up until it becomes completely white (a "flashbang" effect).When playing back the file on a PC, the transition from black to fully white takes about 1-2 seconds (accumulating over several frames).Key Observations & What I've Already Tested: DCMIPP Output is OK: I have a live preview on an LCD screen displaying the input buffers direct

CubeMX 6.16.0's "Memory Management" Tool assumes Rx_PoolSection size to coincide with the Eth "Rx Buffers Length" - is that correct? I used CubeMX 6.16.0 to create a project for an STM32 H755ZI-Q.Then I opted to use the Tools -> "Memory Management" tool and afterwards enabled the ETH [ethernet] component. This automatically generated the required sections in the "Memory Management" tool. Great.Then I enabled LwIP [with RTOS and CMSIS v2] and generated code.Compiling this code worked - linking however did not. It told me the contents of Rx_PoolSection were too big, i.e. the section too small: EBoxNG3_CM7.elf section `.Rx_PoolSection' will not fit in region `Rx_PoolSection'region `Rx_PoolSection' overflowed by 225668  The buffer for the RX_POOL is declared in CM7\LWIP\Target\ethernetif.c:98:#define ETH_RX_BUFFER_CNT 12U LWIP_MEMPOOL_DECLARE(RX_POOL, ETH_RX_BUFFER_CNT, sizeof(RxBuff_t), "Zero-copy RX PBUF pool");with__attribute__((section(".Rx_PoolSection"))) extern

Split from this post.  Hi @massimogPVS ,   Please let me check and confirm whether your assumption about missing updates in RM0454 compared to RM0444 is correct. I have submitted an internal ticket on this topic: 227689 (this is an internal tracking number and is not accessible or usable by customers). -Amel Hello,I am also using STM32G0B0 and running into hardfaults when attempting to modify flash in the second bank. Can ST please provide an update?

Hello Team,I am trying to integrate the VL53L8CX ToF sensor with the NXP KW47 EVK using the I²C interface.For the sensor software, I am using the publicly available VL53L8CX SDK from the following GitHub repository:https://github.com/stm32duino/VL53L8CXI have ported the required platform-specific code to the KW47.According to the VL53L8CX datasheet, I have configured the I²C address as 0x52/0x53 (8-bit write/read address). However, during communication, the sensor is NACKing the address at the 9th clock pulse of SCL.I have also verified the sensor supply voltages and confirmed that the required voltage levels are present.I have attached a few snapshots of the I²C frame captured using a picoscope while debugging, particularly showing the address phase and the NACK occurring on the 9th SCL clock.Could you please help me identify what could be causing the NACK during the I²C address phase?Thank you.

Hi all,I'm recording 16 kHz mono audio from the on-board digital MEMS mic (MP23DB01HP) of the STM32N6570-DK using the BSP's MDF path (MDF1, filter 0, PE2 MDF1_CCK0, PE8 MDF1_DATIN0, GPDMA1 channel 0, SPI mode, falling edge). The recording runs next to a camera/ISP pipeline, an NPU model and an H.264 encoder, so I want the audio path to cost as little CPU as possible and sound clean.Current setup (BSP defaults for 16 kHz)Kernel clock: IC8 from PLL4 = 50 MHz (HSI-based), PROCDIV = 2, CCKDIV = 12, so the PDM clock is about 2.08 MHz CIC: Sinc4, R = 32; reshape filter on, ÷4 (total decimation 128) Gain +2 (about +6 dB); HPF 0.000625 × fPCM (about 10 Hz) Async continuous acquisition, circular DMA into a 16 KB bufferWhat I triedI built a test firmware that records one clip per MDF configuration (5 s each, one config per boot) and compared them offline. Configs: Sinc4 vs Sinc5 R = 32 (gain steps −7, −8, −9), HPF at 10, 20, 40 and 152 Hz, a PLL4 retune to 81.92 MHz with IC8 ÷ 10 for an exact 2.

Greetings,I am working with nucleo_c5a3zg board and I am using zephyr RTOS for my project. I wanted to interface the sd card and try to do some data logging. I had a adafruit data logger shield which can fit on nucleo_c5a3zg board and there is a shield support in zephyr. When i build and uploaded the code i am getting a error that CMD8 is not supported. During debugging i found out that there is no state change on MISO line. Just to check if my code is wrong i tried same code with nucleo_f446re board and it works fine.Following is the capture from saleae loggic for necleo_c5a3zg board. I can provide other details like code, .dts file, etc.If someone can help me solve this issue it would be much appreciated.

Could you please clarify whether the ST67W611M1 supports IEEE 802.11k/v/r and Wi-Fi roaming?If it does, could you please point me to the documentation that describes this support? I could not find any information about it in the datasheet, user manual, or ST Wiki.

ETH is obviously a dual-clock peripheral, and some of the registers are most probably behind a synchronizer, in the MII clock domain. It’s not unlikely that reading some of those registers imposes waitstates. Writing may not, but then those are subject to the Successive write operations to the same register might not be fully taken into account erratum (which hints at the fact that there’s a 4-MII-clock synchronization mechanism, at least for writing).Can ST confirm or deny, whether reading and/or writing ETH registers imposes waitstates, and in case of yes, can ST please list related registers and also quantify number of waitstates. Here’s why.In particular, we need this to be quantified for the ‘F4xx, but for other families it would be a bonus to have this, too.Thanks,JW

Hello,I am a Master's student comparing FreeRTOS and Zephyr on the Cortex-M33 of the STM32MP257F-DK, with Linux running on the Cortex-A35. I measure task timing on the M33 with the DWT cycle counter and an oscilloscope, and I want a second core running a fixed bare-metal load in parallel to see how it affects the M33. A few things I could not find in the documentation:1. Cortex-M0+ as load generator. Can the M0+ run its own firmware at the same time as the M33 (and Linux on the A35)? Can it exchange data with the M33 (shared memory, mailbox, other), and which memories can it access? Who starts it?2. GPIOs for the M33. I need 2 or 3 pins that the M33 can toggle freely to measure with the oscilloscope. Which pins of the DK can be given to the M33, and what has to be changed (RIF, device tree)?3. Firmware already on the M33. Does the DK ship with any firmware running on the M33 (for example USB-PD, as I saw reported for the EV1)? Can I load my own firmware without breaking the board?4. Cy