STM32H7R/S MPU documentation lacking details
Hi everyone !
Following this webpage about running touch gfx on H7R/S series I have seen two things that I think can be interresting to add.
https://support.touchgfx.com/docs/development/scenarios/running-graphics-on-stm32h7r
1 - ERRATA FOR GXFMMU
following ES0596 errata document section 2.2.17 basically says that if GFXMMU isn’t used (clock not enabled) the user should mark the region as Device or Non-cacheable with eXecute Never (XN). I tjinh it can be good to add this as a important info because this leads to CPU stalls that are very hard and the issue isn’t simple to fing for new users of Cortex M7 and graphical line microcontroller of ST
2 - MPU FOR SRAM SHAREABLE
If I follow the MPU table given by the page I see that region 5 is ‘SHAREABLE’ and ‘CACHEABLE’ . Reading many documentation and forum threads about the Cortex M7 I discovered that if the region is ‘SHAREABLE’ the region isn’t cached and it leads to performace hit . In a normal scenario (SRAM for variables and DMA buffers in a specific section non-cached) why we would need to specify ‘SHAREABLE’ . Can someone describe me this ? . And is the website correct about this region 5 ?
Have a nice day !