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I'm investigating a suspected flash corruption/ECC issue on an STM32H743.A read from flash address 0x081F0000 consistently causes a fault. The problem is that I'm not fully confident that the fault status registers can be trusted after the event, so I'm looking for a diagnostic approach that does not rely entirely on the captured fault information.Known facts:Accessing 0x081F0000 triggers a fault. ECC_FA2R does not show a failing address. STM32H7 flash ECC is evaluated only when flash is read. ECC granularity is 32 bytes (256 bits).My main question is:If I suspect flash corruption or an ECC problem, but do not fully trust the contents of CFSR, HFSR, BFAR, SR2, or ECC_FA2R after the fault, what is the recommended way to diagnose the problem?Would you:Perform a controlled BusFault-protected flash scan in 32-byte steps? Use HAL_FLASHEx_ComputeCRC() over the suspect region? Dump the entire flash bank via SWD/JTAG and verify externally? Use some other method?Has anyone seen a corrupted flas

I am trying to do OTA programming modifications using the DUAL bank feature of my STM32U575 IC with 1Mbyte of memory.I have successfully done this when the program starts in BANK 1 and I reflash BANK 2. I change the User Option byte to OB_SWAP_BANK_ENABLE and the board reboots and successfully runs from BANK 2.Now, on the next firmware update, programming BANK 1 when I am operating from BANK 2 the HAL_FLASH_Program command fails on the first byte.The erase code is attached and it is very similar to others I have found on GIT for other products. Does the U5 have an inherent defect? any help would be greatly appreciated.

Title shortened from:"With the STM32U545RE, unable to erase the correct Flash Bank, using HAL_FLASHEx_Erase(), when attempting to switch from Bank2 to Bank1".Please keep the title short. Testing is done with the Nulceo-U545RE-Q board having 512KB Flash organized in two Banks. Each Bank has 32 pages of 8KB each. Flash Bank1: 0-31 pages. Flash Bank2: 32-63 pages. I could switch-over from Firmware-Version1 executing in Bank1 to Firmware-Version2 executing in Bank2. I verified that Firmware-Version2 was executing correctly even after hardware reset and power cycle.Attempting to switch-over  from Firmware-Version2 executing in Bank2 to Firmware-Version3 executing in Bank1 fails as I end up erasing the Bank with the currently executing software(Firmware-Version2). I checked the setting of the SWAP_BANK bit and then erased the Bank, using the code below:  /* Get the boot configuration status */ HAL_FLASHEx_OBGetConfig(&OBInit); /* Check Swap Flash banks statu

Hi, Could you please confirm whether an external NFC antenna can be connected to the X-NUCLEO-NFC08A1 board? I see P200 and P202 in the schematic, but it is not clear to me whether these are intended for external antenna connection or only for optional/test points. If an external antenna can be used, could you explain how the on-board etched PCB antenna should be disconnected from the ST25R3916B antenna path, where the external antenna should be connected instead, and what antenna inductance or electrical parameters should be targeted before tuning the matching network?Thanks!Best regards, Jose 

Hello team, Another day, new same issue. :pensive_face:I have setup the DCMIPP PIPE 1 for the stm32n6570 DK, so that it dumps frames in address 0x34200000 which maps to SRAM3 begin address I have enabled bothe the memories SRAM3 and SRAM4 but with out software erase, I used the MX tool for project generation , I goal is to mimic the Continous Mode example provided by ST, I have read about the appilication notes getting started with DCMIPP and the afew sections of intrest form the RM for the deve board on the topic. I however face the challenge  as stated in the Post Title, there Is are no interrups being called yet I set up the global intterrups for both the Pixel pipe and the CSI interfacing, "Still as shown in in the generated files" and set the clocks for the DCMIPP is set to 300Mhz and the CSI interface I had to manualy try setting up the  input clock freq for the IMX335 module to 20Mz as the MX tool does not provide for its setting, but I have this code commented out as there was

We are currently working on a project using the STM32H750IBT6 microcontroller interfaced with a single-bank Quad SPI NOR Flash (MT25QL512ABB) on our custom board. The QSPI interface is operational.However, we are facing an issue with the external loader. While the same external loader setup works correctly with the STM32H750 development board using the same two MT25QL512ABB Flash memories, it fails to function on our custom board.Development board QSPI schematic: Our custom board QSPI schematic: For reference, we are used the external loader implementation for development board from the following link: https://controllerstech.com/w25q-flash-series-part-8-quadspi-external-loader/ We request your support in:Verifying if our schematic connections for the QSPI interface may be contributing to the issue.Identifying any possible hardware or configuration-related causes for the external loader failure.

Hello,I am working with the STM32N6570-DK board and the MB1854B camera module.I am using the ST-provided example code:https://github.com/STMicroelectronics/STM32CubeN6/tree/main/Projects/STM32N6570-DK/Applications/DCMIPP/DCMIPP_ContinuousMode This example works fine — I can display the live camera feed on the LCD.Now I want to enable the HDR (High Dynamic Range) feature of the MB1854B sensor.My questions are:Which part of the example code needs to be modified to enable HDR?Is there a register configuration to switch the sensor to HDR mode?Is there an ST-provided driver or initialization sequence for HDR mode example?I am looking for guidance or documentation on which registers to configure and where to modify the code so that the captured image is in HDR mode and displayed properly on the LCD.Thanks in advance!

Hi We are developing a board with the STM32U073CCT6 CPU. Would it be possible to use a crystal with the following characteristics for the LSE?32.768KHz Cl=6pF/ESR=50kRIn this case, what would be the recommended capacitor values?BRGilberto 

I have a Nucleo-H753ZI board for testing purposes. I used CubeMX to configure SPI4 as a slave. You can see the configuration code below. SPI4_TX is assigned to DMA1 Stream 3, Medium priority, SPI4_RX is assigned to DMA1 Stream 0, medium priority.I have a SPI master attached to the SPI4 which works as intended, i checked that on the oscilloscope. The Master transmits 1 Byte, wait for 50µs, reads another 4 bytes and based on the content of that 4 bytes, continues to clock more bytes in or out. The clock frequency is 12,5 MHz and 680ns pause between each byte. In my testcode below, the globaldata[4] = 10; defines that 10 more bytes will be clocked by the master. So the entire frame will contain 15 bytes.I am now executing three different variations of code leading to surprising results. When calling HAL_SPI_Receive_DMA, the function HAL_SPI_RxCpltCallback is called as expected. When calling HAL_SPI_TransmitReceive_DMA, the function HAL_SPI_TxRxCpltCallback is called as expected. But when

Hello ST export:This is the first time we've used the L9305 chip in our project. The peripheral hardware circuitry is now all set up. I'd like to know whether ST has a standard recommended initialization procedure for the SPI interface of this chip. (such as who is first for BIST or diagnostic comparators)And I have another question: the status and results for BIST are in the EXCEPTION1 register D[8:7], is it correct? Shouldn't it be D[10:9]? 

We refer to the coating requirements in the newly updated AN5231 Cover Glass Guidelines for Single-Zone Time-of-Flight Sensor.Section 4.3 states “Additional coatings are not recommended.” Section 5.2 states “IR ink can be used over exclusion areas.” Table 3 under Section 7 states “Adding ARC can improve transmittance.”There appears to be an inconsistency. How should we interpret this? Are ARC coatings and IR ink permitted? Per AN5231, Section 3.1 and 7 recommend an IR transmittance target of 87%, and Section 4.2 defines the minimum requirement as ≥85%. Could you advise if 85% transmittance meets compliance? Polycarbonate typically achieves ~85% IR transmittance and is included in the guideline’s recommended material list.If we apply ARC coating to boost transmittance, this brings us back to the first question.    

Hello, I am trying to connect to the STM32F072C8T6 microcontroller via USB in the STM32CubeProgrammer, however I am getting:"Device is under read out protection ! If you want to disable RDP please reconnect with Read Unprotect enabled"So, when I check the Read Unprotect (MCU) checkbox, I get:"Please Power off Power on your device."After turning the power off/on, I see the same messages. I cannot connect to the MCU via USB in the STM32CubeProgrammer.I have tried different versions of STM32CubeProgrammer:v2.16.0v2.15.0v.2.13.0v.2.10.0v.2.8.0Moreover I tried on second computer with Windows 11 and I have the same issue.I'm trying to connect my custom board, but I also checked another hardware board (BluePill ) with the same STM32F072C8T6 MCU and it doesn't work either.Interestingly, using the DFU-util v0.8 program I can connect to the MCU and successfully read/write memory:  

Hi I probably found a bug in STM32CubeMXCubeIDE = v2.1.1CubeMX = v6.17.0While configuring FMC like this. This code is generated. The Timing.AddressHoldTime is set to 15 instead of 2 as configured in CubeMXstatic void MX_FMC_Init(void){ /* USER CODE BEGIN FMC_Init 0 */ /* USER CODE END FMC_Init 0 */ FMC_NORSRAM_TimingTypeDef Timing = {0}; /* USER CODE BEGIN FMC_Init 1 */ /* USER CODE END FMC_Init 1 */ /** Perform the SRAM1 memory initialization sequence */ hsram1.Instance = FMC_NORSRAM_DEVICE; hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE; /* hsram1.Init */ hsram1.Init.NSBank = FMC_NORSRAM_BANK1; hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE; hsram1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM; hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16; hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE; hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW; hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS; hsram1.Init.WriteOperation = FM

I am using ADXL203  analog inclinometer. I would to compensate the offset variation with temperature.As the ADXL203 itself does not have an internal temperature sensor, could you give me any advice on how to measure the temperature?Thank anybody for the attention.GF 

hifor stm32G4 series, if MCU option byte IWDG_SW equal TRUE, and the software start the IWDG by calling HAL_IWDG_Init(),when a system reset happen( for example, call HAL_NVIC_SystemReset() or IWDG reset), will IWDG stop counting before  next time initialization?  

Hello, I have a STM32F401RCT connected to a ST25R100.In the ioc file I enabled the X-CUBE-NFC9 library with all the necesary dependencies.All the IOs also have pins assigned to them.Plus Pull ups enabled on the IRQ (open drain) and NFC_Reset.Currently I have found out that it crashes somewhere after MX_X_CUBE_NFC9_Init();ret code: 0NFC BSP COM = 100Welcome to X-NUCLEO-NFC09A1 entered error handlerThis is what I get in my console. I added some printfs in the code already.When I run it in debug mode to check were it calls the error handler it for some reason does not hit the error handler but it gets stuck in stm32F4xx_il_usb.c; when I click pauze, this seems rather odd.HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num){ __IO uint32_t count = 0U; /* Wait for AHB master IDLE state. */ do { count++; if (count > HAL_USB_TIMEOUT) { return HAL_TIMEOUT; } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); /* Flush TX Fifo

Hi, I met a strange issue of ADC overrun during flash erase.The ADC is configured with circular DMA+TIM3 triggered at 1khz:static void ADC_Config(void) { /* Enable clock */ RCC->AHBENR |= RCC_AHBENR_DMA1EN; RCC->APBENR2 |= RCC_APBENR2_ADCEN; RCC->APBENR1 |= RCC_APBENR1_TIM3EN; /* ADC Init */ ADC1->CR |= ADC_CR_ADVREGEN; uint32_t tick = SysTick->VAL; /* Startup delay */ while ((tick - SysTick->VAL) < 960); /* Calibration */ ADC1->CR |= ADC_CR_ADCAL; while (ADC1->CR & ADC_CR_ADCAL); /* TIM3 trigger, DMA enable */ ADC1->CFGR1 = ADC_CFGR1_EXTEN_0 | 3 << ADC_CFGR1_EXTSEL_Pos | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN; /* Use 14MHz ADC clock */ ADC1->CFGR2 = ADC_CFGR2_CKMODE_0; /* Enable overrun interrupt */ ADC1->IER = ADC_IER_OVRIE; /* Long sampling time */ ADC1->SMPR = ADC_SMPR_SMP1_0 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_2; /* Vref and Tint enable */ ADC1->CHSELR = ADC_CHSELR_CHSEL

I am trying to set up an STMWB55CGUx device for THREAD. I want to set it up to have no log or CLI interface on any UART. When I select the FTD THREAD application type the CFG_CLI_UART setting is still requiring a UART to be able to auto generate a hw_uart.c file that is useless to me. This essentially blocks off a UART without editing files that could be overwritten via a re-generation. Is there any fix apart from manually editing auto-generated code? STM32CubeIDE v1.18.1STM32CubeMX v6.12.1

HiI'm looking for STM32 Nucleo boards or similar microcontroller boards that have embedded SIM (eSIM) capabilities. However, I haven't been able to find any boards that directly support eSIM integration. Are there any Nucleo boards that are compatible with eSIM modules like ST4SIM, and how can I identify or find them?Thanks and Regards@avbST 

HI How are you!I am using the SAI interface on the STM32MP257F-DK to connect directly to an external ADC and acquire data in frame mode. I have assigned SAI3 to the M33 domain and run the firmware under FreeRTOS. Despite following all resource isolation configurations specified in the reference manual and conducting a full week of detailed debugging and security settings, launching the M33 firmware remotely from the A35 Linux domain always results in an IAC error. Is it not possible to assign the SAI peripheral to the M33 core?  thanks !

We wanted to migrate our project to the new C5 MCU family, requiring the use of the new app STM32CubeMX2.In our project, we rely on quite a lot of features from FreeRTOS, for example the function `xTaskGetIdleTaskHandle()`.This function gets compiled only if the variable `INCLUDE_xTaskGetIdleTaskHandle` is defined and set to 1, but by default its value is 0.In our project, when used with CubeMX1, we defined this variable in a /* USER CODE BEGIN 1 */. But with th new project structure enforced by CubeMX2, we no longer have user code blocks in that configuration file, and any regeneration in CubeMX2 will override any user change (well, we have a prompt saying the file was edited, but no smart-merge).From CubeMX2, it is not possible to set this include variable (checked “Core → Advanced API Selector → More”). Therefore, the only (hacky) solution I see is to set this include variable to 1 in CMakeLists.txt. IMO, this is not a solution but a workaround.Either CubeMX2 should manage all confi

Hi, according STM32H743 datasheet VDDLDO pin in BGA packages can be supplied independently from VDD pins. The problem is that on STM32H743VIH BGA package VDDLDO and VDD physically shorted in the package. Is the datasheet misleading or I’m missing  something?  

Hi ,I am currently working with the NUCLEO-N657X0-Q board and the STM32N6570-DK board. I am deploying and testing my machine learning models using STM32Cube AI Studio.I have noticed something unusual. The model runs successfully on all target boards except the NUCLEO-N657X0-Q when the NPU is enabled. I am not sure why this is happening and would appreciate any insights or suggestions from the community.Another issue is that the NUCLEO-N657X0-Q shows significantly higher inference/execution times compared to the other boards. Surprisingly, even a Cortex-M7-based board appears to perform better in some cases. This is unexpected, especially considering the capabilities of the Cortex-M55 and NPU.Has anyone experienced similar behavior with the NUCLEO-N657X0-Q? Are there any known configuration issues, performance settings, memory considerations, or NPU-related limitations that I should check?Any help or guidance would be greatly appreciated.Thank you!

Good morning,I have found contradictory information regarding the bypass requirements of the SMPS integrated in the microcontroller.In particular, the datasheet, section 3.4.4, states that 60 µF are required, implemented as 4 × 15 µF.However, this information appears to contradict what is stated in AN5967 (Table 4)  and in the Nucleo reference design (MB1940-N657x0Q-C02).My question is:Are the 20 µF stated in AN5967 and used in the Nucleo board sufficient to ensure proper operation of the SMPS?Best regards,Federico Filosomi

when I try to clean I get this error: Errors running builder 'CDT Builder' on project 'SomeProject'.Cannot invoke "com.st.stm32cube.common.mx.registry.IIdeHelper.getRootProject(org.eclipse.core.resources.IProject)" because the return value of "com.st.stm32cube.common.mx.registry.MxRegistry.getIdeHelper()" is nullWhen I try to program (by pressing Core), I get an error about the ELF missing:Program file does not exist …. SomeProject.elf not foundYet, in Run configurations, “Project: “ and “C/C++ Application:” are correctly set (AFAIK). I don’t understand how to re-set this up. It was set up prior to me, so I’m at a loss right now. Am I supposed to set build configurations before handling the run config, or something? I look at build config and it shows basically the same info… so I’m just confused ATP. Also I know for sure this code works, or did at one point, and haven’t encountered these issues. It’s been a long time since switching to this branch. I tried resetting the program, selec