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I'm looking into the best way to control the brightness of an LED load using PWM from an STM32 and would appreciate some advice on the practical side of the implementation.My understanding is that the average brightness can be controlled by changing the PWM duty cycle while keeping the LED supply voltage constant. For example, increasing the duty cycle should increase the average current and therefore the perceived brightness.What I'm less certain about is choosing an appropriate PWM frequency. A very low frequency could potentially result in visible flicker, while a much higher frequency increases the number of switching events.For a longer LED load, I'm also wondering whether it is better to keep the STM32 PWM output isolated from the actual LED current path using a dedicated MOSFET or LED driver.If anyone has implemented PWM-controlled LED lighting with an STM32, what PWM frequency and timer configuration have you found to be a good starting point?I'm particularly interested in the

Hi there, I am trying to to set up IEEE 1588 PTP time synchronisation with the Netx Duo IP-Stack. I want to port the STM32N6 example (https://github.com/STMicroelectronics/STM32CubeN6/tree/main/Projects/NUCLEO-N657X0-Q/Applications/NetXDuo/Nx_PTP_Client) to my STM32H563 / Nucleo-H563ZI.To my understanding, the H5 Series support PTP and should be able to run the example. The programm runs and prints out the MAC-clock, but the time does not increment and stays always on the same value of 0 seconds and 0 nanoseconds.I also tried to examine the PPS Signal on PG8 with an oscilloscope but as there is no running MAC clock, I get no PPS Signal.To fix this issue I tried different clock increments, thread-priorities. My guess is that the PTP clock in the MAC and the PPS output have to be activated seperately, but I wonder how? Thanks

I’m using an Infineon SEMPER NOR flash (JEDEC manufacturer ID 0x34; S28HS512T) with the STM32H7S78-DK XSPI2 interface. The bootloader uses STM32 External Memory Manager’s SFDP NOR driver, configured as EXTMEM_LINK_CONFIG_8LINES. The device has a hybrid sector map, and I’m updating mapped sectors from firmware stored on an SD card.The updater compares each logical sector, erases sectors marked for update, then writes the corresponding firmware data. Block-protection setup reports success: CLPEF (0x82), writes to CFR3V and STR1V (0x71), and a DYB unprotect write (0xE1) all return HAL_OK.For sector index 33, at address 0x00040000, size 262144 bytes, erase returns EXTMEM_OK (the measured duration was 0 ms). The subsequent write fails before any page-program command is sent: the driver’s initial WIP poll times out after 5 seconds.FW erase begin idx=33 logical=0x00040000 cmd=0x00040000 size=262144FW erase end idx=33 ... status=0 elapsed_ms=0FW write begin idx=33 addr=0x00040000 ... bytes=262

I am experiencing a critical issue with the hardware video encoder (VENC) on the STM32N6 when processing low-light frames.Setup: Sensor: IMX335 connected to STM32N6 Capture Pipeline: DCMIPP configured in 1080p@15FPS capturing and writing to RAM in RGB565 format. Encoder Input: The same RGB565 buffers are passed to the VENC. Storage: The encoded H.264 stream is saved directly to an SD card. The Problem:When the camera enters a dark environment (very low-light conditions) and I manually reduce the Gain/Exposure to very low values (where the image should be almost completely black), the video recorded on the SD card starts to progressively brighten up until it becomes completely white (a "flashbang" effect).When playing back the file on a PC, the transition from black to fully white takes about 1-2 seconds (accumulating over several frames).Key Observations & What I've Already Tested: DCMIPP Output is OK: I have a live preview on an LCD screen displaying the input buffers direct

CubeMX 6.16.0's "Memory Management" Tool assumes Rx_PoolSection size to coincide with the Eth "Rx Buffers Length" - is that correct? I used CubeMX 6.16.0 to create a project for an STM32 H755ZI-Q.Then I opted to use the Tools -> "Memory Management" tool and afterwards enabled the ETH [ethernet] component. This automatically generated the required sections in the "Memory Management" tool. Great.Then I enabled LwIP [with RTOS and CMSIS v2] and generated code.Compiling this code worked - linking however did not. It told me the contents of Rx_PoolSection were too big, i.e. the section too small: EBoxNG3_CM7.elf section `.Rx_PoolSection' will not fit in region `Rx_PoolSection'region `Rx_PoolSection' overflowed by 225668  The buffer for the RX_POOL is declared in CM7\LWIP\Target\ethernetif.c:98:#define ETH_RX_BUFFER_CNT 12U LWIP_MEMPOOL_DECLARE(RX_POOL, ETH_RX_BUFFER_CNT, sizeof(RxBuff_t), "Zero-copy RX PBUF pool");with__attribute__((section(".Rx_PoolSection"))) extern

Hello Team,I am trying to integrate the VL53L8CX ToF sensor with the NXP KW47 EVK using the I²C interface.For the sensor software, I am using the publicly available VL53L8CX SDK from the following GitHub repository:https://github.com/stm32duino/VL53L8CXI have ported the required platform-specific code to the KW47.According to the VL53L8CX datasheet, I have configured the I²C address as 0x52/0x53 (8-bit write/read address). However, during communication, the sensor is NACKing the address at the 9th clock pulse of SCL.I have also verified the sensor supply voltages and confirmed that the required voltage levels are present.I have attached a few snapshots of the I²C frame captured using a picoscope while debugging, particularly showing the address phase and the NACK occurring on the 9th SCL clock.Could you please help me identify what could be causing the NACK during the I²C address phase?Thank you.

Dear ST Community,I am on the STM32WL55CCUX and am facing an issue with both the SubGHz radio initialization and the external 32 MHz TCXO/HSE32 clock.I have a working STM32WL55JC1 board for comparison. The same/general SubGHz software flow works correctly on the JC1, whereas the custom CCUX board exhibits the following two problems:The SubGHz radio remains permanently/continuously in the RF BUSY state. The external 32 MHz, 3.3 V TCXO is not being powered through PB0/VDDTCXO, and HSERDY does not become active.I would like ST's assistance in determining whether these two symptoms are related to the RF power/reset/TCXO sequencing, a CCUX-specific requirement, or a hardware/configuration issue. This is the current analysis so far                         JC1             CCUXPB0/TCXO supply Active 0 VHSERDY 1 0ErrorCode 0 0x02RFBUSYS after init 0 1STDBY_RC PASS F

I am working on stm32 C5A3ZG platform for one of my projects. I want to use SD card for data logging. I have working SD card module. I tried to use it with nucleo_c5a3zg board using zephyr RTOS and there infrastructure of file management that code is not working on this C5 controller which uses HAL2 driver. It works on other STM32 controllers which use HAL driver.I tried to create a project in STM32CubeMX2 but couldn’t find configuration for SDMMC over SPI which would be required to interface SD card.I checked in STM example library https://dev.st.com/stm32-example-library/result?filters=N4IgpgHghgtgDgGzAOVmEAuA2gXQDQgwDGArpliAMoAqAsgMwBMAwgKwj4gBGA9lAE4ATcpxgBLQYKQB3AemyjSAEX5iAbmH4iCvAYIAKUIgGsoAc3m4Cg1Rv7UAnnEs4AvkA but was not able to find any sample or SD card.Can someone provide a sample code to me otherwise i have to look for potentially changing the platform and move to some other controller.

Hi all,I'm recording 16 kHz mono audio from the on-board digital MEMS mic (MP23DB01HP) of the STM32N6570-DK using the BSP's MDF path (MDF1, filter 0, PE2 MDF1_CCK0, PE8 MDF1_DATIN0, GPDMA1 channel 0, SPI mode, falling edge). The recording runs next to a camera/ISP pipeline, an NPU model and an H.264 encoder, so I want the audio path to cost as little CPU as possible and sound clean.Current setup (BSP defaults for 16 kHz)Kernel clock: IC8 from PLL4 = 50 MHz (HSI-based), PROCDIV = 2, CCKDIV = 12, so the PDM clock is about 2.08 MHz CIC: Sinc4, R = 32; reshape filter on, ÷4 (total decimation 128) Gain +2 (about +6 dB); HPF 0.000625 × fPCM (about 10 Hz) Async continuous acquisition, circular DMA into a 16 KB bufferWhat I triedI built a test firmware that records one clip per MDF configuration (5 s each, one config per boot) and compared them offline. Configs: Sinc4 vs Sinc5 R = 32 (gain steps −7, −8, −9), HPF at 10, 20, 40 and 152 Hz, a PLL4 retune to 81.92 MHz with IC8 ÷ 10 for an exact 2.

Greetings,I am working with nucleo_c5a3zg board and I am using zephyr RTOS for my project. I wanted to interface the sd card and try to do some data logging. I had a adafruit data logger shield which can fit on nucleo_c5a3zg board and there is a shield support in zephyr. When i build and uploaded the code i am getting a error that CMD8 is not supported. During debugging i found out that there is no state change on MISO line. Just to check if my code is wrong i tried same code with nucleo_f446re board and it works fine.Following is the capture from saleae loggic for necleo_c5a3zg board. I can provide other details like code, .dts file, etc.If someone can help me solve this issue it would be much appreciated.

Just now:Notifications of 2 different posts marked as ‘Best Answer’ for the same question at, essentially, the same time. Also had similar earlier this morning:This time five ‘Best’ answers! What’s going on?! ​@nbsown and ​@Rafo were you, perhaps, trying to mark multiple post all as ‘Best Answer’ ?Or did you just change your minds ?

Hello,I am a Master's student comparing FreeRTOS and Zephyr on the Cortex-M33 of the STM32MP257F-DK, with Linux running on the Cortex-A35. I measure task timing on the M33 with the DWT cycle counter and an oscilloscope, and I want a second core running a fixed bare-metal load in parallel to see how it affects the M33. A few things I could not find in the documentation:1. Cortex-M0+ as load generator. Can the M0+ run its own firmware at the same time as the M33 (and Linux on the A35)? Can it exchange data with the M33 (shared memory, mailbox, other), and which memories can it access? Who starts it?2. GPIOs for the M33. I need 2 or 3 pins that the M33 can toggle freely to measure with the oscilloscope. Which pins of the DK can be given to the M33, and what has to be changed (RIF, device tree)?3. Firmware already on the M33. Does the DK ship with any firmware running on the M33 (for example USB-PD, as I saw reported for the EV1)? Can I load my own firmware without breaking the board?4. Cy

Product / board: STM32MP257F-EV1, MB1936 revision, configuration [A35-TD or M33-TD]SummaryThe board worked for one session after two hardware changes, then stopped booting. LD6, LD5 and LD11 light. LD3 and LD4 do not. The Boot ROM gives no response over UART or USB.What was changedA PDM microphone was wired to PA6/PA7 by a wire tap at R169/R175 (MDF1). This was our own design decision, not based on any ST recommendation. A MAX98357A speaker amplifier was added on SAI2A (PJ11, PJ3, PJ12 at AF4), with matching device-tree changes.What I have checkedCheck Result NRST (B1) 3.3 V idle, 0 V pressed, 3.3 V after release VDDIO 3.3 V 1V8 1.8 V VDDCPU 0.8 V VDDCORE 0.8 V VDDGPU 0 V (not treated as a fault) VDD_DDR 0.037 V (not treated as a fault) VDDA1V8_AON 1.8 V  VDD3V3USB 3.3 V  HSE Not checked; no accessible probe point Boot ROM tests (SW1 all OPEN)STM32_Programmer_CLI -l detects the ST-LINK V3. -c port=/dev/ttyACM0 br=115200 and -c port=/dev/ttyACM1 br=11520

Hi,I have this toolchain and need to generate a SBOM:STM IDE v1.18STM IDE GNU Tools for STM32 13.3.Rel1STM32Cube FW_L4 V1.18.1, specified in `\*.ioc` fileSTM32_USB_Device_Library (v2.0_Cube)STM32CubeMX 6.14.0FreeRTOS (10.3.1)How could I turn this into a SBOM?I tried scanning the folder strucutre with syft but this did not work. I then tried to manually make a syft Json file, but when testing for vulnerabiliteies (like e.g. here ) i could not find them. I am not sure how to specify the above components, such that they get recognized by the automated search engine (Grype).I found a statement from ST, that SBOMs will be provided for their products, but I could not find said lists for my toolchain. Some repositories on the GitHub Repositores contain `sbom_cdx.json`. However, I struggle to connect my Toolchain components to the repositories on Github (there are over 700 and for example "stm32cubeIDE" returns 0). Any help is appreciated! Related Links:Wikip

Hii’m triyng to use USBX audio class on nucleo-h563zi. i have succed to make PC to recognise the board like a controller audio but windows have problem to start the device (error code 10), problem 0xA status:  0xC0440027i’m stuck at this fase unfortunately also i think there are some missing files in the middleware directory, in the example provided by ST UX_Device_Audio2.0_Playback (not sure is related to the error to start device)there is this code: VOID USBD_AUDIO_PlaybackStreamChange(UX_DEVICE_CLASS_AUDIO_STREAM *audio_play_stream, ULONG alternate_setting){ /* USER CODE BEGIN USBD_AUDIO_PlaybackStreamChange */ /* Do nothing if alternate setting is 0 (stream closed). */ if (alternate_setting == 0) { return; } BufferCtl.state = PLAY_BUFFER_OFFSET_UNKNOWN; /* Start reception (stream opened). */ ux_device_class_audio_reception_start(audio_play_stream); /* USER CODE END USBD_AUDIO_PlaybackStreamChange */ return;}the function ux_device_c

Hello,We use two ST67W611M1 modules with STM32H563 hosts (bare-metal, SPI host interface at 10 MHz; reproduced at 20 and 40 MHz as well). Both modules run the NCP/AT build reporting AT version:1.0.0.1 (Mar 20 2026 09:32:19), sdk 2.0.106. One module is a SoftAP with a TCP server, the other is a station that opens one TCP client link to it.We have a reproducible failure on the station module that we would like you to look at, because its timing is too regular to be load-related.Symptom. Exactly 60 s after AT+CIPSTART succeeds (about 62 s after +CW:CONNECTED), the station module stops serving the SPI host: the next AT+CIPSEND=0,<n> never gets its > prompt, the RDY (data-ready) line stays low, and every subsequent AT command goes unanswered. There are no SPI framing errors on our side (header sync and length checks are clean up to the last frame). The Wi-Fi association and the DHCP lease survive — the AP module's AT+CWLIF still lists the station — so it is the SPI/AT service insid

I could not find any literature about this so I decided to post on community. When I activate ISM303DAC I experience noise on other parts of the board. At first, I thought this is caused by the communication, but it is not. Also, there is no noise when only the accelerometer is enabled. My theory, the noise is caused by the set/reset function...I haven’t been able to prove my theory, yet. I am working on it. So, I am asking if anybody experienced the same problem. Thanks for the feedback. Your thoughts and comments are welcome.  

This is the follow-up to my 2023 thread, which is now closed for replies:https://community.st.com/stm32cubeide-mcus-28/azurertos-netxduo-unable-to-download-16k-or-larger-image-using-web-http-client-secure-124990Short version: the stall is in the ST NetX Ethernet glue driver (`nx_stm32_eth_driver.c`), not in NetX Duo, and not a packet-pool sizing problem. The fix is about 40 lines and still applies to the current `STMicroelectronics/stm32-mw-netxduo` main branch, which has the same driver code. I have filed it with ST as a bug with the full write-up and patch: https://github.com/STMicroelectronics/stm32-mw-netxduo/issues/1 **Symptom (from the original thread)**HTTPS downloads of 16 KB or more via `nx_web_http_client` + NetX Secure stalled on every attempt on F417, F429 and H723. Plain HTTP downloaded multi-MB files fine with the same pool. After a stall the socket stayed ESTABLISHED and the pool showed fewer free packets than expected, which I wrongly reported as "free_packets corrupted

I was playing around with CubeMX2 (Version: 1.1.1) and some examples.I took the current STM32CubeC5 FreeRTOS low-power example (git tag cadccf7), generated the CMake project, compiled it in STM32Cube for VSCode and started debugging it… which worked fine initially.I then wanted to enable the “Debug” options inside “HALE System Init” in CubeMX2.After re-generating the project code and compiling it, it did not run properly anymore.It always became stuck inside “ASSERT_DBG_STATE(htim->global_state, HAL_TIM_STATE_ACTIVE);” in “HAL_TIM_Stop_IT” located in “stm32c5xx_hal_tim.c”.The callstack was like this:mx_freertos_app.c → app_freertos_post_sleep → mx_pwr_exit_low_power → mx_rcc_init → HAL_UpdateCoreClock → HAL_InitTick (in stm32_hal_timebase_tim.c ) → HAL_TIM_Stop_IT My actual questions:Is this just a “bug” in the example? If so, how should the code inside “app_freertos_post_sleep” or around it actually look like? If this is a problem somewhere else - How can I fix it or when will it b

Student capstone: VL53L1X vs VL53L5CX for drop-off detection on a wearable aid for blind usersHi ST team,I'm an Electrical Engineering student at BCIT in Vancouver, and my capstone team is building a wearable obstacle detection aid for blind users. A chest-mounted depth camera handles obstacles, and we want dedicated ToF sensors for drop-offs like stairs going down. The sensors would be mounted at chest or waist height, angled down at the floor about 1.5 m ahead of the user, and read over I2C by an ESP32 so drop-off warnings don't depend on the main processor.We're still deciding between 2 to 3 VL53L1X single-point sensors and one VL53L5CX, and would really appreciate a quick recommendation. Our main concerns:- Measuring the floor at a shallow angle from about 2 m away. Which part handles that geometry more reliably, and what would you suggest for field of view or ROI settings?- Dark, glossy, or polished floors (tile, vinyl, gym floors) that may return a weak or specular signal.- Readi

I have been writing some code to recover from the NMI after reading unwritten OTP addresses but I found a bit of a snag when checking that the Address listed in FLASH_ECCDETR is what I would expect after a read.The Table 42 of the H503 reference manual (RM0492 Rev 2) lists a minimum ADDR_ECC offset of 0x0600. I was a little unsure what exactly this meant but `HAL_FLASHEx_GetEccInfo()` clearly runs:// FLASH_ADDRESS_OFFSET_OTP is defined as 0x600 as you would expect herepData->Address = (FLASH_OTP_BASE + ((addr_reg - FLASH_ADDRESS_OFFSET_OTP) * 4U)) & 0xFFFFFFFFU;Seems simple enough then - the number is just which OTP word triggered the error minus 0x600.Except the actual offset I am seeing in the address field is 0x200 instead of 0x600.Reading an unwritten OTP at 0x08FFF010 gives me an ADDR_ECC of 0x204, reading 0x08FFF020 gives me 0x208, and so on...Is this an error in the Reference Manual and HAL? Should the listed value be 0x200 or am I missing something here? Thanks!

HI everyone,I am using STWINBX1 sensor board. i am facing a problem while converting the .DAT file  to CSV file. i have recorded the data on SD car using the ST BLE sensor app. the converted data seems to be corrupted. i have used only one sensor  iis3dwb_acc for data acquistion. is there any easier way for the conversion of the data. i have used the python code which comes with the FP-sns-datalog2-1.2.1 (older version) called hsdatalog_data_export. and  i am using the latest DATALOG2 version 3.4 on the board. as we cant record with older versions.thanks in advance 

Hello,while investigating a HardFault on an STM32U385RGT6Q, I noticed several differences in the code generated by newer CubeMX versions.At the moment I am unsure whether I have overlooked a configuration dependency or whether this is an actual CubeMX code generation issue.Environment:MCU: STM32U385RGT6QFlash Configuration:    Total Flash : 1 MB    Bank 1      : 512 kB    Bank 2      : 512 kBApplication Memory Layout:    0x08000000 - 0x080FDFFF  Application Flash (1016 kB)    0x080FE000 - 0x080FFFFF  Parameter Storage (8 kB)Protection Settings:    Application Area:    Read Only by Privileged Code Only    Parameter Storage:    Read / Write by any Privileged level In CubeMX Version 6.15.0 Flash and MPU initialisation look like this: static void MX_FLASH_Init(void){ /* USER CODE BEGIN FLASH_Init 0 */ /* USER CODE END FLASH_Init 0 */ FLASH_OBProgramInitTypeDef pOBInit = {0}; FLASH_BBAttributesTypeDef FLASH_BBSecInitStruct = {0}; /* USER CODE BEGIN FLASH_Init 1 */ /* USER CODE END FLA

Hello,We are designing a PCB around the STM32N657B0 (VFBGA198) using the internal SMPS. VDDSMPS and VDDA18PMU are fed from a dedicated 1.8 V buck, with VDDA18PMU filtered from the same rail, as per Figure 2 in DS14791.For our derating and fault analysis we need the absolute maximum ratings of these two pins, and we cannot find them in any current ST document:DS14791 Rev 11 (Sep 2026), Table 22 “Voltage characteristics”: no VDDSMPS or VDDA18PMU row. The “VDDA18 – VSS, 1.98 V” row lists only VDDA18PLL, VDDA18CSI, VDDA18USB and VDDA18ADC. DS14791 Rev 11, Table 25 “General operating conditions”: VDDSMPS and VDDA18PMU are 1.62 / 1.8 / 1.89 V. DS14791 Rev 11, Table 29 “Characteristics of SMPS step-down”: the input is called “VDDA18”, 1.62 to 1.89 V. AN5967 Rev 6, AN6000 Rev 1 and RM0486 Rev 4: no absolute maximum for either pin.QuestionsWhat are the absolute maximum ratings (min and max) for VDDSMPS and VDDA18PMU? Does the “VDDA18 – VSS, 1.98 V” row in Table 22 also cover VDDSMPS and VDDA18P