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Hello!I'm using an STM32H747 MCU on a custom board. We typically flash the STM32 from a Jetson using stm32flash over UART, and this process has worked reliably on over 50 boards.However, I recently discovered that a couple of boards from a new manufacturing batch, using the same MCU, are experiencing issues with the CM4 core failing to boot.To investigate, I used STM32CubeProgrammer to inspect the flash memory directly and found a consistent gap. The CM4 firmware starts at 0x08100000, but the region from 0x08100040 to 0x081002F0 remains erased every time the firmware is programmed using stm32flash.Interestingly, the memory regions before and after this gap appear to be programmed correctly, and the same issue occurs consistently on the affected boards.So far, i have found two MCU’s where this problem occurs and both have the same chunk of memory missing. I am able to fully flash successfully using the JTrace. Its just when we try to flash with  the stm32flash tool that this fails.I was

Hi,I’m facing an issue when I’m trying to modify multiple Option Bytes on the STM32G473 with one call to STM32_Programmer_CLI.The issue seems to occur whenever the BOOT_LOCK-parameter is part of the call.The call looks like this:STM32_Programmer_CLI --connect port=SWD --optionbytes BOR_LEV=0x3 nRST_STOP=0x0 nRST_STDBY=0x0 nRST_SHDW=0x0 IWDG_SW=0x1 IWDG_STOP=0x1 IWDG_STDBY=0x1 WWDG_SW=0x1 BFB2=0x0 DBANK=0x1 nBOOT1=0x1 SRAM_PE=0x1 CCMSRAM_RST=0x1 nSWBOOT0=0x0 nBOOT0=0x1 NRST_MODE=0x3 IRHEN=0x1 PCROP1_STRT=0x7FFF PCROP1_END=0x0 PCROP_RDP=0x0 WRP1A_STRT=0x7F WRP1A_END=0x0 WRP1B_STRT=0x7F WRP1B_END=0x0 PCROP2_STRT=0x7FFF PCROP2_END=0x0 WRP2A_STRT=0x7F WRP2A_END=0x0 WRP2B_STRT=0x7F WRP2B_END=0x0 SEC_SIZE1=0x0 SEC_SIZE2=0x0 BOOT_LOCK=0x1When BOOT_LOCK is part of it, the execution stops with the error “Unable to get core ID” .When it’s not, everything works fine.The issue is also reproducible when it’s just one other parameter besides BOOT_LOCK, eg. STM32_Programmer_CLI --connect port=SWD --op

ProblemOur team builds a product UI on TouchGFX 4.26.0. A growing number of our developers use Apple Silicon (arm64) macOS machines, but we can only build inside a Linux x86-64 container. The reason is that all host-side TouchGFX artifacts we depend on are shipped as Linux ELF x86-64 or Windows only, there is no macOS build. These are the four files we need macOS versions of: touchgfx/lib/linux/libtouchgfx.atouchgfx/3rdparty/libjpeg/lib/linux/libjpeg.atouchgfx/framework/tools/imageconvert/build/linux/imageconvert.outtouchgfx/framework/tools/fontconvert/build/linux/fontconvert.out Items 1, 2 are what we statically link; items 3, 4 are standalone CLI tools we run at build time. We already have the matching framework/include headers from the 4.26.0 release, so nothing else is needed on our side.Expected / requestedA macOS (Darwin) build of exactly those four artifacts, ideally as universal binaries (arm64 + x86_64). These are the same portable C++ sources you already compile for Linux and

 Hello,We are using the STM32F207ZGT6 in our production boards and have identified two different silicon revision groups: REV_ID = 0x201F (revision 2/3): DFU works correctly. REV_ID = 0x203F (revision 4/5): DFU does not work. The two board versions have an identical schematic, including the USB interface. However, the DFU functionality works with the older silicon revision and fails with the newer one.Could anyone from STMicroelectronics clarify the following points? What are the detailed differences between silicon revisions 2/3 (0x201F) and 4/5 (0x203F)? Were any changes made to the USB OTG FS peripheral, clock startup, oscillator circuitry, electrical characteristics, or system boot behavior? When was silicon revision 4 (0x203F) first introduced into production? Is there a silicon revision history, release note, or PCN documenting these changes? Any information or documentation from ST that could help us identify the root cause would be greatly appreciated.Thank you for your

Board / softwareSTM32N6570-DK (MB1939), STM32N657X0H3Q STM32Cube FW_N6 V1.4.1, ThreadX + USBX from the package (not X-CUBE) STM32CubeIDE, load-and-run development flow (ELF downloaded into internal SRAM by the debugger; no FSBL, no XIP, no external loader) USB2_OTG_HS configured as Host_HS on CN17, internal HS PHY OTGPHY2 clock = RCC_USBPHY2CLKSOURCE_HSE_DIRECT, 24 MHz HSE crystal CPU 600 MHz, AHB 200 MHz USBX: UX_MAX_DEVICES 8, UX_APP_MEM_POOL_SIZE 98304, USBX_MEMORY_STACK_SIZE 65536, only the CDC-ACM class registeredWhat worksA USB 2.0 mass-storage device (HP, VID 0x03F0 / PID 0x2003) enumerates reliably and repeatedly:[usb] idVendor : 0x03F0[usb] idProduct : 0x2003[usb] bcdUSB : 0x0210[usb] bMaxPacketSize0 : 64[usb] speed : HIGH[usb] state : ADDRESSED[usb] -- interface 0 class 0x08 (mass storage) 0x06/0x50[usb] ep 0x81 BULK IN mps 512[usb] ep 0x02 BULK OUT mps 512UX_DEVICE_ENUMERATION_FAILURE here is e

I found an ADC regression on `STM32H563RG` after upgrading from `STM32Cube FW_H5 v1.5.1` to `v1.6.0`.Setup:- MCU: `STM32H563RG`- Old package: `STM32Cube FW_H5 v1.5.1`- New package: `STM32Cube FW_H5 v1.6.0`- CubeMX: `6.17.0`Symptom:- I sample multiple external channels on `ADC2`, including `ADC2_INP0`.- Before the upgrade, `ADC2_INP0` measured correctly.- After the upgrade, `ADC2_INP0` no longer reflects the actual GPIO input voltage, while the other ADC2 channels still behave correctly.This is not a sampling-time or rank-order issue. The problem follows `ADC2_INP0` specifically.The regression appears to come from a change in the LL helper for Channel 0 GPIO switch control.In older FW_H5 code, `LL_ADC_EnableChannel0_GPIO()` always set `ADC1->OR.OP0`, regardless of the ADC instance passed in.In FW_H5 v1.6.0, that helper was changed to set `ADCx->OR.OP0` instead. On STM32H563, that breaks `ADC2_INP0`.What fixes the problem in my testing is:- still enabling Channel 0 GPIO switch cont

This workshop provides a practical introduction to the STM32C5 microcontroller series and shows how it supports entry-level and mainstream designs. It explains how the STM32C5 series combines high performance, rich integration, and cost efficiency.The workshop also explains how the STM32Cube ecosystem supports faster development. It covers STM32CubeMX2, STM32 HAL2, and STM32CubeIDE for VS Code, and shows how these tools help developers evaluate, configure, and develop applications more efficiently. This approach can accelerate time to market and reduce development effort.Practical examples show how existing STM32 projects can transition smoothly to STM32C5. They also show how these projects can benefit from the latest toolchain improvements.What you'll learnUnderstand the STM32C5 architecture, features, and positioning Assess whether it fits your application or customer project requirements Get started quickly with STM32C5 using the upgraded STM32Cube ecosystem Explore developer tips a

Summary This article describes how to use the HAL2 project format when developing STM32 applications. It explains what changes with HAL2 compared to the HAL1 framework, how the new project structure affects user code, and how to work safely with code generation. The article shows that, under HAL2, main.c becomes the central user code area and is no longer overwritten by code generation. The generated layer becomes more portable and easier to reuse. The article also shows how to use the code generation menu and the Code Preview feature to protect user code, how the new format maps into a VS Code workspace, and how drivers, handles and interrupt handlers are organized in HAL2. SummaryIntroductionPrerequisites1. File structure1.1 HAL11.2 HAL21.3 Comparison between HAL1 and HAL2ConclusionRelated links Introduction The introduction of HAL2 marks a significant evolution in the STM32Cube software ecosystem. From a driver point of view, HAL2 improves performance and memory footprint

When training a standard model (e.g. `mobilenetv2_a035`, `pretrained: True`) for image classification on a custom dataset with 2 classes, training crashes at the first epoch:ValueError: Arguments `target` and `output` must have the same rank (ndim).Received: target.shape=(None,), output.shape=(None, 2)I’m working with: Windows, Python 3.12, TensorFlow/Keras 3My minimal user_config.yaml to reproduce the error:model:  model_name: mobilenetv2_a035  input_shape: (224, 224, 3)  pretrained: Truedataset:  class_names: [class_a, class_b]training:  dropout: 0.3 My analysis is the following:1. `get_mobilenetv2()` (`image_classification/tf/src/models/mobilenetv2.py`) correctly builds a binary head when`num_classes == 2`: `Dense(1, activation="sigmoid")`.2. `api.get_model()` saves the freshly built model and sets `cfg.model.model_path`.3. Because `model_path` is now set, `ICTrainer.prepare()` (`tf/src/training/ic_trainer.py`) calls `change_model_number_of_classes(self.model, self.num_classes)`.4.

Hi everyone, I am encountering an issue with the STM32G0B1RCTB microcontroller, specifically related to the "errata" concerning its dual-bank memory architecture.My project uses firmware structured as follows: a bootloader located at the beginning of the flash (0x08000000), an application located at 0x08006000, and a CRC data section—generated during the post-build process to ensure firmware integrity—placed at the end of the flash (0x0803F000).I need to keep the prefetch feature enabled; however, due to a known issue inherent to this microcontroller, the system crashes once the firmware exceeds a certain size.To resolve this, I decided to modify the option bytes to set the device to "single-bank" mode, which would allow me to keep the prefetch feature enabled.However, when the microcontroller resets (triggered by `FLASH->CR |= FLASH_CR_OBL_LAUNCH;`) to apply the new option bytes, the bootloader executes correctly (as it is located at the start of the flash), but the jump to the app

I am not sure but if this is a minor issue or should be fixed when working with STM32U083CCT6 MCU and those line is inside stm32u0xx_hal.c file.Note: I can not add picture or drag it i dont know why. * @brief Configure the Flash prefetch and the Instruction cache,* the time base source, NVIC and any required global low level hardware* by calling the HAL_MspInit() callback function to be optionally defined in user file* stm32g0xx_hal_msp.c. In the automatic generated comment lines it state that it was in stm32g0xx_hal_msp.c. If those kind of minor issues should be reported somewhere else , i use that place if i come accross the same situation again.(I am working with stm32u0xx by the way via CubeMX selection and code generation)

By the way can i achive UX_Device_CDC_ACM_Standalone with my MCU? I am not sure if i can achieve this. In some LAB videos, they can achieve Standalone HID but i am not sure if it can be done for CDC_ACM standalone? I am struggling with CDC_ACM trying to do standalone without threadx, only usng usbx.Split from the post: STM32U083CCT6 HAL_StatusTypeDef Description Section | Community

Are the 4 MSbits of the M24M04E-F slave address completely fixed at 1010? So incompatible with another I2C peripheral on the same bus sharing the same 4 MSbits slave address, yes? Is there a clever way around this? (I know it can be changed on the M24M02E-F.)

  I am noticing a particular issue while measuring the internal temperature sensor using ADC on an STM32H743. Since my Vref tends to vary with temperature, I am internally sampling the Vref to measure the correct reference to the temperature sensing unit.  In the main codeblock that calculates the temperature from the ADC values, I am using the built-in calibrated values for 30C and 110C. Please see below.  My ADC is setup in the following way. static void MX_ADC3_Init(void){  hadc3.Instance = ADC3;  hadc3.Init.Resolution = ADC_RESOLUTION_16B;  hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE;  hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;  hadc3.Init.LowPowerAutoWait = DISABLE;  hadc3.Init.ContinuousConvMode = DISABLE;  hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;   // 64 MHz / 4 = 16 MHz  // --- CRITICAL POLLING SEQUENCE CORRECTIONS ---  hadc3.Init.NbrOfConversion = 2;  hadc3.Init.DiscontinuousConvMode = ENABLE/*DISABLE*/; // Pauses sequence after each rank  hadc3.Init.ExternalTrigCon

Hello, Our setup uses a VL53L9-based board with an STM32N657 (NUCLEO-N657X0-Q). The sensor streams RAW8 over one data lane at 1 Gbps on VC0. We are using ST’s driver, and 54 × 42 at 100 fps works well.We would like to connect three or four sensors to the N657’s CSI-2 receiver and trigger them through SYNC_IN at staggered times, so their frames do not overlap on the link. Each frame occupies the link for about 0.24 ms of the 10 ms period.We checked the receiver’s lane-state flags between frames. The clock lane remains in high-speed mode throughout streaming, while the data lane returns to the stop state (LP-11). This suggests that the sensors keep driving both lanes, which would prevent them from sharing the same lanes without a MIPI switch or bridge.Could you please clarify the following?Clock-lane mode: Can the VL53L9CX use non-continuous clock mode and return its clock lane to LP-11 between frames? If so, which register or firmware patch enables this? Pin states: Can the MIPI clock a

Hello ST Support Team,We are developing a custom evaluation board using the STM32C5A3REG6 MCU and ISM330DHCX IMU.We would like to connect our board directly to MEMS Studio via USB without using the STEVAL-MKI109D motherboard.We have reviewed UM3420 and UM3233, but would like to clarify the following: Can MEMS Studio recognize a custom STM32-based board? Is implementing the ProfiMEMS serial command protocol sufficient? Does MEMS Studio require specific USB VID/PID values, board identification commands, or firmware version responses? Is the complete communication protocol or compatible firmware source code available? Can the MLC configuration, training workflow, and sensor data visualization functions be used with custom hardware? Thank you.

Hello, I mistakenly programmed the HSM enable record into the host core DCF area at address 0x29F81A10. Could this introduce any risk of incorrect configuration? I found that I can overwrite the incorrect DCF record by programming all 0xFF. However, I am concerned that the programmed 0xFF may differ from the 0xFF of an unprogrammed blank device. Could you advise whether this operation is valid?

Hello,I am attempting to run the OpenAMP_TTY_echo_CM33_NonSecure example following this guide Modify, rebuild and reload the firmware but run into the following error when attempting to run the example.IDE ErrorError in final launch sequence: Failed pre launchFailed pre launchFirmware remoteproc load failed, please:    1. make sure that /lib/firmware on your target has space    2. make sure that /lib/firmware has write access   > you can open a Console View for this..Serial Terminal Logs[   82.376063] remoteproc remoteproc0: powering up m33[   82.378336] remoteproc remoteproc0: Image is corrupted (bad magic)[   82.381610] remoteproc remoteproc0: Boot failed: -22Run configuration I have attempted to use the .elf file as suggested here https://community.st.com/t5/stm32-mpus-software-development/error-using-cubeide-ro-run-an-example-application-for-the/m-p/721825 but get the a similar IDE error with the followin

Hello everyone! I am following the tutorial on st wiki on how to work with STM32MP257F-DK board. Everything was going pretty good, until the “Develop on Arm® Cortex®-M33” part. This is a really important part for me, because the main reason I chose this MPU is because of the additional low-power cortex M33 and M0 co-processors. The part where I am stuck is “Modify, rebuild and reload the firmware for A35-TD flavor”. I have successfully built the “*_sign.bin” file and populated the board with it by using the “Run_Configuration” button. However past 78% the process stops and shows an error that states:“Error in final launch sequence:Failed pre launchFailed pre launchFirmware remoteproc load failed, please:     1. make sure that /lib/firmware on your target has space     2. make sure that /lib/firmware has write access   > you can open a Console View for this..”In the STM32MP2 system a log of these messages are displayed:“[ 2321.306087] remoteproc remoteproc0: powering up m0 [ 2321.307

 1. Executive SummaryDuring evaluation of the vienna_stm32g474 reference project, a data-rate decoupling effect was identified in the main PFC voltage control loop. The physical DC-link voltage feedback structure (VOLTAGE_ADC_DC_IN_PHY) is calculated inside a 2 kHz telemetry task (TIM7), but it is consumed by the main cascaded controller (DPC_LCT_PFC_Ctrl) operating within the 20 kHz interrupt loop (TIM2).Although the raw ADC data is sampled at 20 kHz (TIM2) and is immediately available in the Data Layer via DPC_CDT_DcVoltageRead(), the conversion to physical units is delayed by the low-frequency task. This feedback latency was previously masked by a 16-bit register truncation error in TIM7, which forced its real execution frequency up to ~8.7 kHz. Testing confirms that relocating the physical voltage scale conversion (DPC_ADC_VoltageDCAdc2PhyProcessData) to the 8 kHz voltage loop task (TIM6) resolves this constraint, optimizing PI controller responsiveness and improving grid current w

I have an IIS3DWB10IS connected to ESP32 host MCU via four-wire SPI.It answers the WHO_AM_I correctly and lets me read out accelerometer values successfully.However, when I want to init it to ODR larger than 20 kHz what corresponds to values 0x6 (40kHz) or 0x7 (80kHz) the read back value is 0x05 (20 kHz)What only could I be doing wrong?Do I need to configure anything beforehands setting the ODR?This is the output of my initialization function:[MINI2] R WHO_AM_I(0x0F)=0x50 expected=0x50[MINI2] BDU enable: R/W CTRL3_C(0x12), wrote=0x44 readback=0x44[MINI2] Self-test positive: configure ODR=80 kHz, FS=50 g, INT1_DRDY_XL=1[MINI2] setup readback CTRL1_XL=0x05 CTRL2_XL=0x00 INT1_CTRL=0x01

RefMan RM0522 version 1.0 seems to conflict with the datasheet DS15137 - Rev 3 and DS15136 - Rev 1.RM0522 Table 23 says that all three calibration values (Vrefint, TS_CAL1 and TS_CAL2) are stored as 32-bit words.Both Datasheets’ sections 5.3.5 specify the Vrefint calibration value as 24-bit. (?! - looks like a mistake)Both Datasheets’ sections 5.3.20 show the TS_CALx values as 16-bit, as in most of other STM32 models.

We used to define STM32 pinout in STM32CubeMx since it's aware of all the possiblilities of the MCU.Then we manually need to transfer the pnout into Altium Designer Schematic. And to keep those in sync when design changes.So we want to automate that step if possible.Thus the question: How can I Import pinout generated from STM32CubeMx into Altium Designer Schematic.

Page 47 Figure 15. GND Plane: GND plan instead of GND planeGuidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs - Application note Can’t attach a screenshot for some reason