Why is the high level range 0.7VDD~VDD and the low level range 0.3VDD~VSS in Table 21 of STM32F103xC, STM32F103xD, STM32F103xE (DS5792 Rev 13), while the rise time in Figure 19 ranges from 10% to 90%?
You can see the rise time of IIC in Figure 48 of <STM32F103xC, STM32F103xD,STM32F103xE DS5792 Rev 13> or Figure 43 of <STM32F103xC STM32F103xD STM32F103xE Rev 5>.
Sorry, I can't open the website.In IIC , the rise time is from 30% to 70%. You can see this in Figure43 of <STM32F103xC, STM32F103xD, STM32F103xE (DS5792 Rev 13)>. But according to what you mean, the maximum of the rise time in IIC is from 10% to 90...
