About vegac

vegac · 2024-06-24

Hello,We have been trying to use the STM32H747I-DISCO to act as a SPI slave which should respond to a command byte, behaving similarly to how a sensor or EEPROM might.That is, the fist byte sent from the master will be a command and our slave device ...

vegac · 2024-06-26

We have found that doing MODIFY_REG(hspi5.Instance->CFG1, SPI_CFG1_UDRCFG, 0); MODIFY_REG(hspi5.Instance->CFG1, SPI_CFG1_UDRDET, 1); At the end of our init function allows us to operate in 8-bit mode correctly (as in, we can respond in the 1s...

vegac · 2024-06-24

I believe this is the same issue seen in https://stackoverflow.com/questions/73037098/stm32-spi-slave-response-to-master-lags-for-several-bytes but that individual was able to rely on using the enabled CRC to act as a buffer byte between the command ...

vegac · 2024-06-24

I was wrong about 32-bits needing to be loaded. 16-bit is enough, and makes it so that I am only 1 byte late. This is still an issue, but does point to it being a race condition with the peripheral instead of something with the FIFO I'd think?

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STM32H7x SPI Slave FIFO data loading

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