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nickbeth · 2024-05-06

We encountered an issue with the SPI3 peripheral on F4xx and F7xx series chips where the RXNE bit of the status register would be set right after enabling the SPI peripheral after re-configuring it.This is clearly impossible as no transaction is perf...

nickbeth · 2024-08-19

Why can we remove the last one? Isn't it needed to ensure the backup region can't be written to?Imagine that, for some reason, we do this:HAL_PWR_EnableBkUpAccess(); __DMB(); std::copy(buffer, buffer + num_bytes, BaseAddress + address); __DMB(); HAL_...

nickbeth · 2024-05-16

Hello @Petr Sladecek,We have double checked that we perform a flush of the RX buffer before disabling the SPI peripheral, and we also read the AN5543 carefully but we are not able to spot any mistakes that we are making. I would like to remind that t...

nickbeth · 2024-05-08

Would love to get someone from ST to take a look at this. @SofLit not sure if you're the right person to tag, if you're not could you please redirect this to whom it may concern? Thanks!

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STM32F7xx/STM32F4xx: SPI3 RXNE is erroneously set after enabling the peripheral

Re: Memory/Instruction barriers before writing to the backup SRAM

Re: STM32F7xx/STM32F4xx: SPI3 RXNE is erroneously set after enabling the peripheral

Re: STM32F7xx/STM32F4xx: SPI3 RXNE is erroneously set after enabling the peripheral