I tracked the problem down to the application code configuring the PLL without first disabling it, so the changes were ignored.Adding the + line fixed it and I could use any JTAG pod.+ LL_RCC_PLL_Disable(); LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOU...

@roger239955_stm1​ I ran into the same problem when using the J-Link. STLink did not show this problem. Power cycling the board restored normal behavior, so it does seem like a clock tree setup, but I haven't had time to dig into it.A work-around i...