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clifford · 2014-03-06

Posted on March 06, 2014 at 19:00Hi all, I'm trying to interface a multi-channel ADC to the F4 series over SPI or perhaps I2S. Need to achieve DMA. I have 256 bits. Can I use a NSS signal that is low for 256 serial clocks? Or do I need to burst bot...

clifford · 2014-03-07

Posted on March 07, 2014 at 10:50Ok I think I understand. So off the falling CS edge trigger the TX DMA for the output and set this to the bit length that you expect to receive with this being clocked in on the RX path as a straight stream. Think th...

clifford · 2014-03-06

Posted on March 06, 2014 at 22:45Thanks for the replies, much appreciated. so in Master mode SPI CS can go low to intiaite the transfer, stay low for 256 continuous clocks and then come high again to signal the end of the transfer? Sorry- I'm not to...

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ST32F4 SPI recieve stream length 256 bits - how must they be framed

Re: ST32F4 SPI recieve stream length 256 bits - how must they be framed

Re: ST32F4 SPI recieve stream length 256 bits - how must they be framed