2014-03-06 10:00 AM
Hi all,
I'm trying to interface a multi-channel ADC to the F4 series over SPI or perhaps I2S. Need to achieve DMA. I have 256 bits. Can I use a NSS signal that is low for 256 serial clocks? Or do I need to burst both the NSS (CS) and SCLK signals so that the interface receives the data in 16-bit packets? Regards, M.2014-03-06 10:10 AM
Having it auto-magically alter CS is a problem, but should should be able to transfer 256-bits in a stream as either 32x 8-bit or 16x 16-bit, and manipulate CS at either end.
2014-03-06 01:20 PM
That is the beauty of DMA, it is fire and forget.
you configure the DMA to point to the buffer, tell it how many transfers, change CS, enable the DMA. Then reset CS in the DMA ISR 255 is far less than the limit of 655352014-03-06 01:45 PM
Thanks for the replies, much appreciated. so in Master mode SPI CS can go low to intiaite the transfer, stay low for 256 continuous clocks and then come high again to signal the end of the transfer?
Sorry- I'm not too au fait with how this balances versus the 16-bit transfer descriptions in the manual.2014-03-06 01:56 PM
The CS/NSS control afforded by the STM32 is unusably awful, it's orders of magnitude easier to drive it via a GPIO, the DMA would fill the SPIx->DR (holding register), and subsequent bytes/words are emitted back-to-back, so you should see your data clocked in a continuous stream.
You'd drive data out to clock the bus, and clock back in the response. You'd need two DMA streams, a TX and a RX one.2014-03-07 01:50 AM
Ok I think I understand.
So off the falling CS edge trigger the TX DMA for the output and set this to the bit length that you expect to receive with this being clocked in on the RX path as a straight stream. Think this makes sense to me. Thanks for your advice, much appreciated.