Posted on December 06, 2016 at 10:41hi David ,the jitter from clock will degrade SNR performance , it's better to use low jitter system clock.regarding the power supply error correction feature , you need to contact with your local ST/distributor of...
Posted on November 15, 2016 at 09:30hi ME,STA309A can handle 192Khz sample rate .according to your hardware configuration, please make sure your bit clock is 12.288Mhz ,due to it's 64FS .and your clock output frequency is strange , please check your...
Posted on October 31, 2016 at 03:22Hi Me ,you can refer to schematic in datasheet page 18 for MCLK connection, it's XTI input. below link is latest datasheet.http://www.st.com/content/ccc/resource/technical/document/datasheet/97/41/d6/a4/6b/2a/40/b...
Posted on October 20, 2016 at 09:12Hi Me ,the Master clock could be the clock that you fed to ADC , since ADC may provide LRCK and BICK to system , then I2S clock must be synchronized with Master clock for STA309A , otherwise you will hear pop corn ...
Posted on October 20, 2016 at 09:05hi Allen,the link of datasheet is below http://www.st.com/content/ccc/resource/technical/document/datasheet/43/57/41/42/e4/e8/43/42/CD00000123.pdf/files/CD00000123.pdf/jcr:content/translations/en.CD00000123.pdfand ...
