Posted on February 20, 2014 at 16:37I am using TIM1 (PWM Mode) to trigger injected adc conversions in dual mode. The ADC clock is set to 72 Mhz (PLL Clock). The ADC sampling is set to 19.5 cycles --> a total conversion time of 19.5 + 12.5 = 32 cy...
Posted on December 18, 2013 at 23:00I am using a STM32F203IGT6 trying to detect low VDD using the PVD feature. This seems simple, but I cannot make it work. My initialization code is below. I start the peripheral clock set the PLS and PVDE bits (...
Posted on February 20, 2014 at 17:38Thanks for the reply. But I don't think that latency explains what i see. If I add 3.5 cycles for maximum latency the total time from PWM rising edge to the conversion of 1 adc channel, it should be (35.5 cycle...
Posted on December 23, 2013 at 14:32The issue is that both VDD and VDDA must be below the threshold for the PVDO bit to be set . This is the case for the brown out as well. The board I have has separate VDD and VDDA. Hence, the BOR and PVD have...
