2014-02-20 07:37 AM
I am using TIM1 (PWM Mode) to trigger injected adc conversions in dual mode. The ADC clock is set to 72 Mhz (PLL Clock). The ADC sampling is set to 19.5 cycles --> a total conversion time of 19.5 + 12.5 = 32 cycles = 444 nsec. For N channels the JEOS interrupt should occur at N * 444 nsec after the rising edge of the PWM.
The problem is that the JEOS interrupt occurs at N * 1.68 usec after the rising edge of the PWM. I have tried this for 1,2 and 3 ADC conversions in the sequence. I have confirmed the correct clock by calling RCC_GetClocksFreq(). I also changed the sampling from 19.5 cycles to 61.5 cycles and the time from PWM rising edge to JEOS changed by the appropriate amount - 578 nsec. Does anyone know what's causing the 1.2usec delay in the ADC conversion2014-02-20 08:07 AM
The reference manual says
''Figure 47. Injected conversion latency 1. The maximum latency value can be found in the electrical characteristics of the STM32F40x and STM32F41x datasheets.'' The datasheet says : tlat(4) Injection trigger conversion latency fADC = 30 MHz - - 0.100 μs - - 3(7)μs 1/fADC (4) Based on characterization, not tested in production. (7) For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67.2014-02-20 08:38 AM
Thanks for the reply. But I don't think that latency explains what i see.
If I add 3.5 cycles for maximum latency the total time from PWM rising edge to the conversion of 1 adc channel, it should be (35.5 cycles) = 493 nsec. I see 1.68 usec. (ADC clock = 72 MHz)2014-02-20 09:06 AM
What part are we talking about, most of the parts have a max ADC clock rate in the 14-18 MHz range.
2014-02-20 09:43 AM
STM32F302RBT6
2014-02-20 10:35 AM
This part has the fast ADC with clocks up to 72MHz