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DavidO · 2023-08-10

With SYSCLK set to 400MHz in MX Clock Configuration there is no problem, but any setting above ~420 up to the maximum of 480Mhz causes the system to 'crash' during initialisation in HAL_RCC_ClockConfig(..). More specifically when or after RCC->CFGR i...

DavidO · 2023-04-20

DavidO · 2023-08-11

Yes, PWR_REGULATOR_VOLTAGE_SCALE0 works. Many thanks. I had to force that setting, though, because it is not available in CubeMx. The key it seems to the higher clock rate is to set the overdrive bit in the SYSCFG power control. This is a feature o...

DavidO · 2023-04-20

Setting the caches ON and speculation enabled, took to figure to 1352, -Os to -O2 to 1868 and taking the frequency to 550MHz to 2136. Running from ITCMRAM will not be a practical option. That is a good result. Many thanks for the help.

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Unable to get maximum SYSCLK of 480MHz on STM32H743XIH

STM32H723: How to achieve the Coremark figure? The published figure is 2778 at 550MHz. My implementation of Coremark at 480Mhz is a mere 327 with GCC ver10.3.1 and the default MX configuration. Is there an article on how to get full speed?

Re: Unable to get maximum SYSCLK of 480MHz on STM32H743XIH

Re: STM32H723: How to achieve the Coremark figure? The published figure is 2778 at 550MHz. My implementation of Coremark at 480Mhz is a mere 327 with GCC ver10.3.1 and the default MX configuration. Is there an article on how to get full speed?