About JLima

JLima · 2019-03-05

Hello everyone,I am having a very strange problem with respect to SPI6 and I am hoping someone can give me some direction. I have configured the SPI6 to be in SPI master mode and I am continuously reading data from a sensor. Everything looks to be f...

JLima · 2018-11-26

Hello everyone,For my current project I need the FreeRTOS+MPU to work on H7. I got it somehow to work with DTCMs. However, when I try to move the complete memory allocation to the AXI SRAMs the FreeRTOS is hanging in the systick handler (there is a f...

JLima · 2019-03-13

Hello @Amel NASRI ,Thanks for the reply. Seems like they are. I am attaching a picture from the clocks. Any other idea? Is there any bug related with the Bus bridges that we have to workaround that is not included in the code generated by CubeMX? Th...

JLima · 2018-12-11

Could someone from ST please reply? This is currently a major blocking problem in my current project

JLima · 2018-12-07

My H7 board has the r1p1 and F7 the r1p0. So I guess the H7 board is even newer. Was there any changes in terms of cache management between these two revisions???

JLima · 2018-12-05

Still stuck with this issue..Anyone from ST that could take a look? What can I still try from the firmware perspective? Since it works with F7, I could imagine is either some difference to the H7 that I am not aware or maybe an HW bug.

JLima · 2018-11-26

Just tried with an STMF7 nucleo board the exactly same example and putting the data in the SRAM1 and it works...It looks to be really H7 specific...

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STM32H7 SPI6 problem

Cache problem with FreeRTOS and MPU

Re: STM32H7 SPI6 problem

Re: Cache problem with FreeRTOS and MPU

Re: Cache problem with FreeRTOS and MPU

Re: Cache problem with FreeRTOS and MPU

Re: Cache problem with FreeRTOS and MPU