About Tim.N

Tim.N · 2024-08-15

Hello!I'm trying to update from v1.11.0 to the latest stack in our firmware for stm32wb5x_BLE_HCILayer_fw.bin to address the errata around the utilizing the PLL, but CPU2 is hard faulting as soon as we invoke SHCI_C2_BLE_Init(...).I can run and load ...

Tim.N · 2024-08-15

Hello!The errata states this as a workaround for this errata:DescriptionWhen CPU1 switches the system clock frequency, the C2HPRE divider may need to be updated according toCPU2 frequency requirements. Changing the C2HPRE divider by CPU1 when CPU2 is...

Tim.N · 2021-07-20

If I invoke "hci_le_set_advertise_enable(0)" after advertising via "hci_le_set_advertise_enable(1)", I can no longer communicate with CPU2 and the C2DS bit inside PWR_EXTSCR is no longer set which indicates it didn't go into a low power state (and th...

Tim.N · 2021-03-29

I've gotten my STM32WB55 into a state where CPU2 is booting into a "wireless firmware" area, but I think it's crashing when it starts. I can no longer talk to FUS inside CPU2:------------------------------------------------------------------- ...

Tim.N · 2020-11-09

Hi -I had been working on getting FUS support for upgrading images integrated into our firmware, and I discovered that my initialization of the CRC peripheral was causing the FUS subsystem to reject all upgrade attempts. I couldn't find any document...

Tim.N · 2024-09-23

Hi Remy -We don't perform BLE connections on our platform so I didn't test that use case; we only ever do BLE advertisement scans. I suspect that maybe the BLE connection path is a bit different since there are harder real-time requirements to meet ...

Tim.N · 2024-09-16

@Remy ISSALYS wrote:Regarding stm32wb5x_BLE_HCI_AdvScan_fw.bin firmware, indeed the ACL buffers are not used as connection is not supported in this variant. Is it a bug then that this variant requires allocation for ACL buffers but cannot use them?

Tim.N · 2024-09-16

I did some testing, and at least for the BLE scanning case, the RADIO does not wake up CPU2 independently of C2BOOT. I wrote some code that prints out whenever C2DS and CRPF in PWR_EXTSCR change along with allowing me to clear C2BOOT on selectable e...

Tim.N · 2024-09-12

Hi Remy -I did read through those, but both the errata and AN5289 do not cover the case where C2BOOT is cleared after having started CPU2, and didn't talk about whether or not inspecting the C2DS bit in conjunction with clearing C2BOOT would be suffi...

Tim.N · 2024-09-11

Note that I'm still keen on knowing if this can be done or not. I'd like to avoid using the SHCI_C2_SetSystemClock(...) call if CPU2 is currently in STOP and cannot wakeup if I clear C2BOOT between usages of CPU2. The call adds a significant power ...

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STM32WB CPU2 hard fault in HCI stack variants in v1.20.0

STM32WB Errata "CPU2 hard fault when changing C2HPRE clock divider in RCC_EXTCFGR on CPU1"

STM32WB55: Does invoking "hci_le_set_advertise_enable(0)" lock CPU2 for anyone else?

Wireless Stack recovery for STM32WB

Is the CRC peripheral used by the FUS services on the STM32WB?

Re: STM32WB Errata "CPU2 hard fault when changing C2HPRE clock divider in RCC_EXTCFGR on CPU1"

Re: STM32WB CPU2 hard fault in HCI stack variants in v1.20.0

Re: STM32WB Errata question for "CPU2 hard fault when changing C2HPRE clock divider in RCC_EXTCFGR register on CPU1"

Re: STM32WB Errata question for "CPU2 hard fault when changing C2HPRE clock divider in RCC_EXTCFGR register on CPU1"

Re: STM32WB Errata question for "CPU2 hard fault when changing C2HPRE clock divider in RCC_EXTCFGR register on CPU1"