Posted on March 13, 2014 at 21:34Can anyone tell me if the following is normal functionality of the RFR register: Processor clock 168 MHz APB1 bus 42 MHz After reading the Receive FiFo and releasing by setting RFOM1 bit to 1 in the RF1R register, we...

Posted on October 23, 2013 at 21:20Using the 3 channels of the SDADC in Single Ended Zero Reference Mode, Gain 1, with a SDREF at 2.5V.  Spec lists gain error of -2.4% to -3.1%, but our devices appear to have a positive gain error of approx +2.8%.  ...

Posted on June 06, 2013 at 13:44I am using the both SDADCs configured as follows: 3 channels configured for injected conversions SDADC2 triggered when SDADC1 is triggered SDADC1 triggered from timer configured for 200 usec Both SDADC1 and 2 configur...