STM32F373 SDADC Gain Error Issue

garyconner9 · ‎2013-10-23

Posted on October 23, 2013 at 21:20

Using the 3 channels of the SDADC in Single Ended Zero Reference Mode, Gain 1, with a SDREF at 2.5V. Spec lists gain error of -2.4% to -3.1%, but our devices appear to have a positive gain error of approx +2.8%. Offset calibration run and offset values in reg CONF0R approx 0x05e3. Measured 1.8241V at ADC input, ADC value reads 0x4030. Per the formula from AN4207, this is equivlent to 1.8768V. According to AN4207, the definition of negative gain error would result in an ADC reading less than the measured value.

Is this an known issue? Is there any way to create this problem in software or extenal hardware?

Thanks

Gary

Igor Cesko · ‎2013-11-19

Posted on November 19, 2013 at 14:29

Probably is there is problem only with the sign of the gain error (question of convention). In this case for fixed input voltage is ADC output data greater than it should be (the transfer characteristic (input voltage on Y-axis, ADC data on X-axis) is below ideal curve).

If the gain error is negative then the ADC can measure voltage slightly below VREFSD.

I will reproduce this above theory on my board with my device to be sure.

Regards

Igor Cesko

Igor Cesko · ‎2013-11-22

Posted on November 22, 2013 at 16:39

I am confirming this gain error sign convention: negative error means that ADC result is higher than expected and the full ADC range is below VREFSD+ voltage. Or by another words: ADC result correspond to lower input voltage than expected.

We will improve the documentation to be more clear.

Regards

Igor