About Franzi.Edo

Franzi.Edo · 2022-09-08

Dear all,I am looking for a reference document listing the resources (timers, RAM, GPIOs, bus clocks etc) that are used by the Bluetooth stack provided byST (stm32wb5x_BLE_Stack_full_fw.bin).Any idea where I can find a complete documentation?Thanks a...

Franzi.Edo · 2021-12-16

Dear All,We are running a graphical application using LTDC and DSI on a STM32L4R9 discovery board. We refresh the display per portions with the DSI peripheral configured in adapted command mode. At the beginning of a portion refresh, we are reconfigu...

Franzi.Edo · 2021-05-21

Hi,I am facing a strange cache problem. I use the DCMI coupled to the DMA in order to acquire an image into the external SDRAM. As indicated in the application note AN4839, I proceed in this way.before to start the DMA transfer I clean the cache (cac...

Franzi.Edo · 2020-04-26

Hi,I have a NUCLEO L552 and I would like to run a very simple program (just blinking a led).I have placed my vector table @ 0x08040000 as described by the data sheet. to program the flash I use the J-Link from Segger. What is strange, is that I canno...

Franzi.Edo · 2019-07-05

Dear all,I am facing to a stm32h743 issue. I have a Nucleo with the stm32H743 Rev Y that work perfectly. Now, I just tried the new Nucleo equipped with the stm32H743 Rev V. As expected, my previous code (Rev Y) does not work on the new device (Rev V)...

Franzi.Edo · 2021-12-16

Hi Jan, thank you for your suggestions. I will try to reallocate the memories in my system in order to let the display buffer alone in the selected memory.Stay tuned. Thank youEdo

Franzi.Edo · 2021-05-23

Hi All,thank you for all your input. I implemented the clean/invalidation by address and on all my hardware (M7 and H7) and things run well.Great support, thank you.Edo

Franzi.Edo · 2020-04-26

Hi Berendi,Correct! I was confused by some documentation.Of course, the NS vector is placed @ 0x08040000. So, in NS mode, no need to operate with additional stuff. Now it works!Thank you

Franzi.Edo · 2019-07-07

forgotten one line ...// Only for Rev. V PWR->CR3 &= ~(PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS); PWR->CR3 |= PWR_CR3_LDOEN; PWR->D3CR &= ~PWR_D3CR_VOS; PWR->D3CR |= PWR_D3CR_VOS_1; while ((PWR->D3CR & PWR_D3CR_VOSRDY)...

Franzi.Edo · 2019-07-07

Thank you Clive and Linas.Problem solved. It was enough to add the following instructions before the PLL set-up. The Clive code was helpful. Thank's// Only for Rev. V PWR->CR3 &= ~(PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS); PWR->CR3 |= ...

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stm32wb5x_BLE_Stack_full_fw.bin (used resources)

stm32l4r5 - LTDC FIFO underrun error

different cache behavior between stm32H7 and stm32F7

stm32l552 bootstrap

stm32H743Y vs stm32H743V

Re: stm32l4r5 - LTDC FIFO underrun error

Re: different cache behavior between stm32H7 and stm32F7

Re: stm32l552 bootstrap

Re: stm32H743Y vs stm32H743V

Re: stm32H743Y vs stm32H743V