About MSpot.1

MSpot.1 · 2020-12-10

I am using the Nucleo-L4r5zi with the octospi peripheral to communicate with a qspi NAND flash chip (W25N01GVZEIG). The octospi peripheral is set up in status polling mode to poll the state of the Write Enable bit in the flash status register. This i...

MSpot.1 · 2020-07-21

I have been trying to get the stm32wb nucleo working with the st7789 lcd but have only observed strange behavior. I have successfully gotten it to work with the stm32f103c8t6 using the code found here. When CPOL=0 on the stm32f103 the screen does not...

MSpot.1 · 2020-12-15

Can you post a screenshot of you spi/dma registers.

MSpot.1 · 2020-12-11

I don't know what is causing this but I have found that polling the status register before during and after a sector erase command gives different values for S1. Before there is a 10ns pulse.During, S1 is high the entire duration as it should beAfter...

MSpot.1 · 2020-07-23

The problem was it was sending 16 clock cycles instead of 8:The ST7789_SPI->DR = datashould have been changed to:*(__IO uint8_t *)&SPI1->DR = datahttps://community.st.com/s/question/0D50X00009Xkfrt/spi-8bit-data-length

User statistics

User Activity

Problems when polling for Write Enable bit in qspi NAND flash status register

STM32WB and st7789 via spi

Re: STM32F767 SPI Bidirectional Receive Mode : More SPI Clocks are output than I expected.

Re: Problems when polling for Write Enable bit in qspi NAND flash status register

Re: STM32WB and st7789 via spi