About Pieter Conradie

Pieter Conradie · 2024-02-14

Hi there!If I interpret table 45 on p. 247 of the reference manual correctly, then the IPCC interrupt is not able to wake up a CPU from STOP mode:Am I correct in my interpretation? If so, is there any other way for CPU1 to wake up CPU2 from STOP mode...

Pieter Conradie · 2023-01-24

Hi there! We are developing a new STM32WL based product that must be compatible with the existing STM32L0 + S2-LP products. It appears that the GFSK data whitening algorithm is different(?). I used an SDR dongle to sniff the raw bytes transmitted...

Pieter Conradie · 2022-09-26

Hi there,I am trying to use the S2-LP as a packet sniffer to receive proprietary RF packets that do not contain a length byte. Is it possible to configure the S2-LP to finish RX by monitoring the RSSI level? How?Thanks in advance,Pieter

Pieter Conradie · 2021-12-06

Hi everyone!I have found that the System Memory (Boot ROM) is always mapped to 0x0000_0000 on the STM32L471RET6 that I'm developing on. The Flash Memory is mapped to 0x0800_0000 as expected but as soon as interrupts are triggered they jump to 0x1FFFF...

Pieter Conradie · 2021-09-13

Hi there!In the S2-LP datasheet it is stated that the typical delay is 40 us: Does this mean that the host microcontroller must use a CSn low delay of at least 40 us when the S2-LP is in STANDBY or SLEEP mode and it wants to send an SPI command to pu...

Pieter Conradie · 2024-02-23

ST support helped me on this. For other people also looking for a solution, this is it:On CPU1:// Enable IPCC CPU1 Wake up interrupt LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_36);On CPU2:// Enable IPCC CPU2 Wake up interrupt LL_C2_EXTI_EnableIT_32_63(LL_EX...

Pieter Conradie · 2023-01-24

OK, I've answered my own question :)The relevant info is contained in NXP AN5070 "Implementing Data Whitening and CRC Verification in Software in Kinetis KW01 Microcontrollers":https://www.nxp.com/docs/en/application-note/AN5070.pdfThe S2-LP implemen...

Pieter Conradie · 2021-12-06

Oh wait! Somewhere I must have lost the plot :pensive_face: Thanks @KnarfB ! I checked again and there was the jumper indeed, pulling BOOT0 high. There must have been a mix up somewhere during the investigation and it's hard to spot (black on black)...

Pieter Conradie · 2021-12-06

Sorry, forgot to add that detail: yes, the BOOT0 pin is low.

Pieter Conradie · 2021-11-08

Hi @Houda GHABRI ,Apologies! :( I had a mixed up installation of STM32CubeProgrammer. The uninstaller for v2.5.0 was missing and I had to go Administrator to get it removed.I can confirm that v2.8.0 actually works :smiling_face_with_smiling_eyes:Kin...

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STM32WL55: IPCC wake up CPU2 from STOP mode? Workarounds?

STM32WL (SX1262) vs S2-LP (CC1101) data whitening algorithm incompatible?

S2-LP: No length byte in RX packet... finish RX on RSSI level?

STM32L471 System Memory always mapped to 0x0000_0000?

CSn low to positive edge SCLK in low power mode state?

Re: STM32WL55: IPCC wake up CPU2 from STOP mode? Workarounds?

Re: STM32WL (SX1262) vs S2-LP (CC1101) data whitening algorithm incompatible?

Re: STM32L471 System Memory always mapped to 0x0000_0000?

Re: STM32L471 System Memory always mapped to 0x0000_0000?

Re: STM32CubeProgrammer is not able to successfully connect to or flash an STM32L471. This is a long-standing problem. I have no problem flashing other STM32L parts such as L051 and I have no problem flashing the L471 using an STLinkv2.