Posted on February 26, 2018 at 19:38I am porting our application from a STM32F779 to a STM32H753 device. Our application looks to run fin if we have the heap located on the DTCM_RAM (the whole 128k is reserved for heap allocation).If the heap is mo...
Posted on February 14, 2018 at 16:26I am trying to read a sector from bank2 while running code from bank1. However, I got and hardfault as soon as I try to perform such read operation.Is it a configuration issue? If yes, any suggestions?
Posted on December 14, 2017 at 15:01I am trying to have device detection code by reading the 'package data' register but I don't get the expected data. I have a STM32F779I-EVAL board with a STM32F779 mcu. I am reading '0xFFFF' at address 0x1FFF 7BF0...
Posted on March 06, 2018 at 14:47 , ,Can you validate for STM32H7 series?I am using , , , ♯ define PACKAGE_BASE (0x58000400+0x124)and the result is not what described for SYSCFG_PKGR of section 12.3.9 from STM32H7 reference manual (en.DM00314099).T...
Posted on March 02, 2018 at 14:21Ibrahim, that was already done. By the way STM, such initilization must be done within STM32Cube H7. Or at least commented out. Also, I added *((__IO uint32_t*)0x51003108) = 0x00000001;It is the same kind of workarou...
Posted on February 28, 2018 at 18:21The problem about wrong computation occurs in a FPU intensitive loop. The problem looks to disappear when I add printf in the middle of the loop (when heap is in SRAM2).Having __DMB() and __DSB() at the same locat...
Posted on February 27, 2018 at 19:29 , ,Clive,Thanks to take time to answer to my question. ,Here couples others details: The malloc-ed memory (the one coming from heap) is not used ,for any DMA buffers. ,Both CPU caches (instruction and data) are ...
Posted on February 16, 2018 at 14:39It looks like this issue was the ECC. Having multiple write operation of the same 32 bytes flash row is just not possible. After adding a caching mechanism in our software driver that calls HAL_FLASH_Program, my i...
