Can both flash bank of STM32H7x3 can be used simultaneously?

[Francois Tremblay]

Posted on February 14, 2018 at 16:26

I am trying to read a sector from bank2 while running code from bank1. However, I got and hardfault as soon as I try to perform such read operation.

Is it a configuration issue? If yes, any suggestions?

[Nesrine M_O]

Posted on February 14, 2018 at 16:58

Hi

francois

,

The Flash memory is divided into two independent banks. The Flash interface can drive different operations at the same time on each bank. A read, program or erase operation can be executed on bank 1 while another read, program or erase operation is executed on bank 2.

Could you please share with us a screen shot about the flash status registers?

-Nesrine-

[Francois Tremblay]

Posted on February 14, 2018 at 17:09

Thanks for quick answer.  Here values of flash registers.

FLASH_CR1:                    0x00000031

FLASH_SR1:                     0x00000000FLASH_OPTCR:               0x00000001FLASH_PRAR_CUR1:      0x000000FFFLASH_SCAR_CUR1:      0x800000FFFLASH_WPSN_CUR1R:   0x000000FFFLASH_CR2:                    0x00000031FLASH_SR2:                    0x00000000FLASH_PRAR_CUR2:     0x000000FFFLASH_SCAR_CUR2:     0x800000FFFLASH_WPSN_CUR2R:  0x000000FFSYSCFG user 0:               0x00AA0000SYSCFG user 6:               0x000000FFSYSCFG user 7:               0x000000FFSYSCFG user 8:               0x00010000SYSCFG user 9:               0x00FF00FFSYSCFG user 10:             0x00FF0000SYSCFG user 11:             0x00010000SYSCFG user 12:             0x00000001

While continuing my investigation on my side, I discovered I could access to some area of the bank2. Here a printf of successfull read operation

flashAddr=0x08100000flashAddr=0x08120000flashAddr=0x08140000flashAddr=0x08160000flashAddr=0x08180000flashAddr=0x081A0000

I got a hardfault handler when I try to read sector 6 (0x081C0000 to

0x081DFFFF

) and sector 7

(0x081E0000 to 0x081FFFFF)

. 

I don't know if it is a coincidence, but they are the only sectors that I previously erased. Is there any special operation that must be done after a sector is erased before being able to read it again? I did not activate any of the read/write protection mechanism.

Thanks

[Nesrine M_O]

Posted on February 15, 2018 at 11:34

Hi

francois

,

Could you please share with us a reduced codethat may help us to observethe behavior in our side?

I thought that it was an ECC error, but it seems not to be the case.

-Nesrine-

[Francois Tremblay]

Posted on February 15, 2018 at 17:39

I am not yet able to reproduce my problem when I try to put together a reduced code function. I will share it when I will be able to reproduce my problem.

It is an application that is already running fine on STM32F779. We have software layer for pseudo filesystem as well as for various non volatile flash memory. 

I customized our software layer to manage STM32H7x3 specific flash memory organization (each write is 32 bytes long and aligned on 32 bytes memory boundary).  Most of our write operation is less than 32 bytes long. We are using a 32 bytes buffer and we pads it with 0xFF. We can have multiple non-overlapping write operations to the same 32 bytes flash memory section. Is it an issue?

Can you provide me more information about how to figure out if it is a ECC problem or not?

[Francois Tremblay]

Posted on February 15, 2018 at 19:50

On hard fault handler hit, HFSR value is 0x40000000. 

So, I look at CFSR and it is set to 0x00008200.

So, I look at BFAR and it is set to 0x081E0007.

The value in BFAR is the address I am trying to read back after an erasing and multiple writing operations to Flash memory.

Why the MCU generates a bus fault (which is escaled to an hardfault) while reading on flash memory?

Thanks

[Francois Tremblay]

Posted on February 16, 2018 at 14:39

It looks like this issue was the ECC. Having multiple write operation of the same 32 bytes flash row is just not possible. After adding a caching mechanism in our software driver that calls HAL_FLASH_Program, my issue is gone.

Thanks for the support.