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I have a board where a secondary CPU can select the STM32MP1's boot mode.  On initial boot, the MP1 boots from NOR flash.  I can then send a command to the secondary CPU which switches the MP1's BOOTx pins to enable engineering boot and resets the MP...
I am currently running in Engineering mode. In this application I am not using Linux on the A7, so I want to enable the trace SWO output from the M4 processor.
I have an application on STM32H750 which runs out of QSPI in XIP mode. After init, I enable the cache with SCB_EnableICache() and SCB_EnableDCache(). After this point, the application goes to a continuous loop which just calls the same small function...
I am trying to configure the Internal Flash (0x08000000, 128KB, cacheable), DTCM RAM (0x20000000, 128KB, non-cacheable), AXI SRAM (0x24000000, 512KB, cacheable), and QSPI (0x90000000, 4MB, cacheable).There is no indication of what parameters might be...
I am trying to read/write the QuadSPI flash on the EV1 from the CM4 controller. I am able to flash and boot from the QuadSPI memory using STM32CubeProgrammer, but when I try to use QuadSPI init code ported from another ST chip (STM32H750), it hangs ...