About VVasi.1

VVasi.1 · 2020-09-17

Hello all,I have an STM32F7508-Discovery board (STM32F750N8H6 MCU) with a custom UI application on top, using LTDC and DMA2D in interrupt mode, and continuously filling the full display with red/blue. The Stm32CubeF7 v1.16.0 is used as an SDK.With th...

VVasi.1 · 2020-06-02

Hello, with a STM32F7508-DK board, all examples using SDRAM have the sysclk to 200MHz, therefore the FMC clock to 100MHz.I am trying to enable sysclk = 216MHz, and FMC = 108MHz, so I followed the SDRAM user manual, and configured the following settin...

VVasi.1 · 2020-09-20

You are right, I finally found an application note from STM where this is explained. See https://www.st.com/content/ccc/resource/technical/document/application_note/group0/25/ca/f9/b4/ae/fc/4e/1e/DM00287603/files/DM00287603.pdf/jcr:content/translatio...

VVasi.1 · 2020-09-18

So, here is an update.I created an MPU region for the display buffers (source and destination for the DMA2D transfers) and disabled the cache on it, hoping this will fix the issue. Unfortunately it did not.Looking in the example, more precisely in (S...

VVasi.1 · 2020-09-18

Thanks for your answer.There is no WFI/SLEEP in my code, so that is not an issue. Also, I have loggers through the fault handlers and they also do not hit.I found out today that disabling the data cache globally fixes the issue, but since I cannot us...

VVasi.1 · 2020-06-03

Many thanks, I missed that. We can consider this topic closed

VVasi.1 · 2020-06-03

Well, that is the point, I did all that and below the computation I did:To support frequencies over 100MHz, I switched to CAS Latency 3 for the SDRAM, also increased the SDRAM GPIOs speed to max (OSPEED HIGH)Then, I analyzed both IS42S32400F-6BL (ISS...

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SDRAM configuration for 216MHz sysclk.

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