Looking for confirmation that the SDRAM data bits can be swapped within their byte lanes (D15..D8, D7..D0) to reduce the routing complexity. We are using vanilla SDRAM (non-DDR), specifically the ISSI IS42S32800G.Thanks.
Thanks for the quick reply. I believe the chip configuration (mode register) is written using the address pins alone, but would welcome any input on that as well.
