Posted on May 17, 2011 at 13:37Sent in a Online Support Request. Got the following response. Dear User, Please find here below latest information concerning the request R10010120 The STM32 FSMC has fairly long requirement on the data set up time wit...
Posted on May 17, 2011 at 13:37In “Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings�? of the“STM32F103xC STM32F103xD STM32F103xE Data Sheet�? (Doc ID 14611 Rev 7) are following entries wrong? tsu(Data_NE) | Data to FSMC_NEx high se...
Posted on May 17, 2011 at 13:36In the RM0008 Reference manual for the STM32F103xx there is a timing diagram for the FSMC SRAM / CRAM Mode 1. How is the FSMC set to Mode 1?
Posted on March 31, 2006 at 20:22In SIEMENS Microcontrolers ApNote AP1609 there is the following statement: When BCLR IEN is used to globally disable interrupts, but an interrupt is still acknowledged before the start of the critical sequence, the s...
