We are using the STM32N657Z0H3Q (142-pin TFBGA package).
CSI behavior in STM32CubeMX is inconsistent across versions:
In older CubeMX versions(1.64), CSI lanes (CSI_D0P/N, CSI_D1P/N, CSI_CKP/CKN, CSI_REXT, etc.) are displayed in the Pinout view, but these signals are not actually assignable to physical pins. They appear as virtual pins only.
In newer CubeMX versions(1.65), CSI is still listed in the peripheral view, but no CSI lane pins are shown at all.
In case, the generated .ioc file contains only virtual signals:
VP_CSI_VS_CSI.Mode=CSI
VP_CSI_VS_CSI.Signal=CSI_VS_CSI
VP_DCMIPP_CSI.Mode=SerialInterface
VP_DCMIPP_CSI.Signal=DCMIPP_CSIOn hardware, when connecting a CSI-2 camera, the following is observed:
DCMIPP and CSI registers initialize correctly,
no LP-to-HS transition on the supposed CSI pins,
ClkAct remains at 0,
CSI interrupts never trigger.
This behavior strongly suggests that the CSI-2 D-PHY pins are not bonded out on the STM32N657Z0H3Q package, even though CubeMX and the datasheet ballout diagrams appear to indicate CSI signals.
Questions / Clarifications Needed:
Is CSI-2 (D-PHY) physically bonded on the STM32N657Z0H3Q (142-pin) package?
If CSI-2 is only exposed as a virtual peripheral on this package and no pin assignment is possible, how is the CSI interface expected to be configured or used on this device?
If CSI-2 is not available on this package, please confirm which orderable part numbers or package variants support CSI-2 with bonded D-PHY lanes.
If CSI is not supported on the 142-pin package, CubeMX and the datasheet should reflect this to avoid confusion.
