STM32H7, STM32F7 cache enabled and MPU disabled

[BVu]

I'm using STM32H723, and STM32F767. CubeMX allows the data cache to be enabed and leave MPU disabled. Is this a valid configuration? Yes, i do know how to configure the MPU. Am i required to enable the MPU and configure all regions to have same attributes if i simply want the whole SRAM to be cacheable?

[TDK · Accepted solution]

> CubeMX allows the data cache to be enabed and leave MPU disabled. Is this a valid configuration?

Yes.

> Am i required to enable the MPU and configure all regions to have same attributes if i simply want the whole SRAM to be cacheable?

No. SRAM is write-back write-allocate cached by default (at least on the H7). You can use the MPU to override this, but don't have to.

https://www.st.com/resource/en/application_note/dm00272913-level-1-cache-on-stm32f7-series-and-stm32h7-series-stmicroelectronics.pdf