Hi all,
I am working with STM32F469ZIT6 and external SDRAM AS4C4M16SA-6TIN SDRAM using FMC (Bank1).
Setup
- HCLK = 180 MHz
- SDRAM clock configurations tested:
- HCLK/2 (90 MHz) → Refresh count = `0x056A`
- HCLK/3 (60 MHz) → Refresh count = `0x0395`
- Data width: 16-bit
- Internal banks: 4
- CAS latency : 2
SDRAM clock has been verified using an oscilloscope and matches expected frequencies.
Test Code
I am writing a pattern to SDRAM and reading it back:
- Write pattern: `0xA1234567 + index`
- Base address: `0xC0000000`
for (uwIndex = 0; uwIndex < BUFFER_SIZE; uwIndex++)
{
*(__IO uint32_t*) (SDRAM_BANK_ADDR + WRITE_READ_ADDR + 4*uwIndex) = aTxBuffer[uwIndex];
}
Read back:
for (uwIndex = 0; uwIndex < BUFFER_SIZE; uwIndex++)
{
aRxBuffer[uwIndex] = *(__IO uint32_t*) (SDRAM_BANK_ADDR + WRITE_READ_ADDR + 4*uwIndex);
}
- Issue (Observed Behavior)
- The read operation does not return the correct written data
- Instead:
- It often returns the previous/last written value.
- The data pattern shows MSB duplication (upper bits repeated), e.g.: 0xA123A123.
Initialization Sequence
static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
{
__IO uint32_t tmpmrd =0;
/* Step 3: Configure a clock configuration enable command */
Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command->AutoRefreshNumber = 1;
Command->ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT);
/* Step 4: Insert 200uS delay */
HAL_Delay(1);
/* Step 5: Configure a PALL (precharge all) command */
Command->CommandMode = FMC_SDRAM_CMD_PALL;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command->AutoRefreshNumber = 1;
Command->ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT);
/* Extended Mode Register Set — required for AS4C4M16SA (drive strength: Full = A1=0) */
Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command->AutoRefreshNumber = 1;
Command->ModeRegisterDefinition = 0x0000; /* Extended MRS: BA0=1 drives bank select; Full drive strength */
HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT);
/* Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_2 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command->AutoRefreshNumber = 1;
Command->ModeRegisterDefinition = tmpmrd;
/* Send the command */
HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT);
/* Step 6 : Configure a Auto-Refresh command */
Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command->AutoRefreshNumber = 8;
Command->ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT);
HAL_Delay(1);
/* Step 6 : Configure a Auto-Refresh command */
Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command->AutoRefreshNumber = 8;
Command->ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT);
/* Step 8: Set the refresh rate counter */
/* (15.62 us x Freq) - 20 */
/* Set the device refresh counter */
HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
}
Observations
Same behavior across:
- Different SDRAM clock settings (90 MHz / 60 MHz)
- Different CAS latencies (2, 3)
- Read burst tested with enabled and disabled
- SDRAM clock verified on oscilloscope
- Write completes without fault
- Read returns incorrect/repeated data pattern
Questions
- Is the Extended Mode Register step valid for this SDRAM?
- Does this symptom (last value + MSB duplication) indicate:
- FMC timing issue?
- Data bus wiring/width issue?
- SDRAM not properly initialized?
- Any known working configuration for this SDRAM with STM32F469?
Attached Files
Full project files are attached (FMC config + test code):
Any insights or debugging suggestions would be greatly appreciated.
Thanks in advance!
