Query about STM32F446 HSE pll setting failure on CubeMX

[SNish]

I am using NucleoF446RE (STM32F446RE) with CubeIDE 1.19.0.
I wish to set PLL  as 16MHz by HSE (STLINK 8MHz MCO).
Because HSI clock is 16MHz.
I had set PLL M/N/P = 4/64/8. 
CubeMX reported P was fail . ]

So I had set P=4. and It makes PLL-CLK = 32MHz

After hal generation I have modified SystemClock_Config as following.

void SystemClock_Config(void)

{

RCC_OscInitTypeDef RCC_OscInitStruct = {0};

RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

/** Configure the main internal regulator output voltage

*/

__HAL_RCC_PWR_CLK_ENABLE();

__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);

/** Initializes the RCC Oscillators according to the specified parameters

* in the RCC_OscInitTypeDef structure.

*/

RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;

RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

RCC_OscInitStruct.PLL.PLLM = 4;

RCC_OscInitStruct.PLL.PLLN = 64;

RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV8;// Hnad modify

RCC_OscInitStruct.PLL.PLLQ = 2;

RCC_OscInitStruct.PLL.PLLR = 3;

if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)

{

Error_Handler();

}

/** Initializes the CPU, AHB and APB buses clocks

*/

RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK

|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;

RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;

RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;

RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)

{

Error_Handler();

}

HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_PLLCLK, RCC_MCODIV_1);

}

Code works fine, I cannot see any condition from RM0390 on this point.
Ple

[TDK · Accepted solution]

Hover over the red area to find an explanation of the issue. In this case:

Unclear why it wants that. Seems like a bug but I could be missing something.

[SNish]

Dear TDK 

I am referring on RM0390 (STM32F446xx).
I cannot find out 24MHz limitation on that.
Is it CubeMX message bundled information only ?

regards

[SNish]

Dear TDK

Thanks for your explanation.
But I cannot see same display on CubeMX.
Is there any method or display setting on CubeMX ?
If 24MHz is minimum limit spec of PLL then I can recognize this issue is
spec.
I have seen Errta and Reference manual please navigate me on this point.

regards

Shigemal

[SNish]

Dear TDK
I cannot see PLL clock minimum frequency spec is 24MHz now,
But it may cause issue of this setting.
My purpose is setting 16MHz clock for application as HSI clock.
I have settled following setup as create 32MHz for MCO and divide to following path.