Synchronization between PWM signal and ADC

[DanielBen]

Hello!

I'm trying to synchronize a PWM signal with an ADC (by TRIGGER OUT EVENT). There are 2 issues:

1. The frequency of the PWM signal is 200 Khz and the frequency of the ADC is 12 Mhz. According to the calculation of 14 cycles (12.5 cycles + sampling time of 1.5 cycles), the conversion time should be 1.16 microseconds, but according to the test, it turns out that this time is 3.16 microseconds (from raising the PWM signal and receiving the result of the conversion). That means there is a gap of 2 microseconds. What could be the reason for the gap and how can it be solved?

2. In addition to this, I tried to perform the experiment with synchronizing a PWM signal with a frequency of 500 Khz. In this mode, the result of the ADC is not received in every cycle, but once every few cycles (in a manner consistent with the PWM signal) - Probably this is due to the 2 microseconds that are added in each cycle.

I would like to know how it is possible to synchronize to a PWM signal with a higher frequency and perform a sample once per cycle (because there is probably some error in the initialization of the system from my side).

I use STM32F103C8T6.

Thanks!

[TDK]

Should be able to get better results than that. How are you measuring these times exactly? And in (2) how are you determining that the ADC only returns every few cycles?

It feels like what you're describing would be consistent with the ADC clock being lower than what you expect. Can you do, say, 5000 continuous dma based conversions and measure the time it takes in order to validate the ADC clock rate?

[DanielBen]

I do all the tests using a scope.
I am attaching a picture of the situation seen in my first question (pic1).
In addition, I attach the situation in the second question (pic2).

In the upper channel (yellow) is the PWM signal.
In the lower channel (pink) is the TOGGLE signal when a value from the ADC is received.

[TDK · Accepted solution]

You've introduced lag due to cpu execution into your setup. Not a good way to measure if you're concerned about a couple μs.

It is not practical to interrupt the cpu at 500 kHz. It can't keep up, thus you only get a trigger once every few cycles.

I'd suggest doing the timing I proposed above to convince yourself that the sampling time is as expected. Taking 5000 samples (or more) will reduce the proportion of overhead to a minimum and convince you the sampling time is as expected.